Data Sheet
Nexperia
CBT3253A
Dual 1-of-4 FET multiplexer/demultiplexer
CBT3253A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 5 — 9 May 2017
5 / 15
9 Static characteristics
Table 6. Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). T
amb
= -40 °C to +85 °C.
Symbol Parameter Conditions Min Typ
[1]
Max Unit
V
IK
input clamping voltage V
CC
= 4.5 V; I
I
= -18 mA - - -1.2 V
V
pass
pass voltage V
I
= V
CC
= 5.0 V; I
O
= -100 μA 3.6 3.9 4.2 V
I
I
input leakage current V
CC
= 5.5 V; V
I
= GND or 5.5 V - - ±1 μA
I
CC
supply current V
CC
= 5.5 V; I
O
= 0 mA;V
I
= V
CC
or GND - - 3 μA
ΔI
CC
additional supply current per input; V
CC
= 5.5 V; one input at 3.4 V,
other inputs at V
CC
or GND
[2]
- - 2.5 mA
C
I
input capacitance control pins; V
I
= 3 V or 0 V - 4.5 - pF
A port; V
O
= 3 V or 0 V; nOE = V
CC
- 11.4 - pFC
io(off)
off-state input/output
capacitance
B port; V
O
= 3 V or 0 V; nOE = V
CC
- 3.8 - pF
C
io(on)
on-state input/output
capacitance
A port and B port - 18.6 - pF
V
CC
= 4.5 V
[3]
V
I
= 0 V; I
I
= 64 mA - 5 7 Ω
V
I
= 0 V; I
I
= 30 mA - 5 7 Ω
R
ON
ON resistance
V
I
= 2.4 V; I
I
= -15 mA - 10 15 Ω
[1] All typical values are measured at V
CC
= 5 V; T
amb
= 25 °C.
[2] This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
[3] Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. The lowest voltage of the two (A or B)
terminals determines the ON resistance.
10 Dynamic characteristics
Table 7. Dynamic characteristics
T
amb
= -40 °C to +85 °C; V
CC
= 4.5 V to 5.5 V; for test circuit, see Figure 6.
Symbol Parameter Conditions Min Max Unit
Sn to nA; see Figure 4
[1]
[2]
1.2 6.2 nst
pd
propagation delay
nA to nBn or nBn to nA; see Figure 4
[1]
[2]
- 0.25 ns
Sn to nBn; see Figure 5
[3]
1.3 6.3 nst
en
enable time
nOE to nA or nBn; see Figure 5
[3]
1.4 6.4 ns
Sn to nBn; see Figure 5
[4]
1.1 7.2 nst
dis
disable time
nOE to nA or nBn; see Figure 5
[4]
1.0 7 ns
[1] This parameter is warranted but not production tested. The propagation delay is based on the RC time constant of the typical ON resistance of the switch
and a load capacitance, when driven by an ideal voltage source (zero output impedance).
[2] t
PLH
and t
PHL
are the same as t
pd
.
[3] t
PZL
and t
PZH
are the same as t
en
.
[4] t
PLZ
and t
PHZ
are the same as t
dis
.