Data Sheet

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1. General description

The HEF4028B is a 4-bit BCD to decimal decoder, a 4-bit BCO to octal decoder with

active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer. The outputs are fully

buffered for best performance.

When used as a BCD to decimal decoder a 1-2-4-8 BCD code applied to inputs A0 to A3

causes the selected output to be HIGH. The other nine outputs will be LOW.

To use the HEF4028B as a BCO to octal decoder, input A3 is an active LOW enable pin

and outputs Y8 and Y9 are not used. A 1-2-4 BCO code applied to inputs A0 to A2 causes

the selected output (Y0 to Y7) to be HIGH. The other seven outputs will be LOW. When

A3 is HIGH outputs (Y0 to Y7) will be forced LOW.

When used as an 8-output (Y0 to Y7) inverting demultiplexer A0 to A2 are used as

address inputs and A3 is the data input. Outputs Y8 and Y9 are not used.

It operates over a recommended V

power supply range of 3 V to 15 V referenced to V

(usually ground). Unused inputs must be connected to V

, V

, or another input.

2. Features and benefits

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 Specified from 40 C to +85 C

 Complies with JEDEC standard JESD 13-B

3. Ordering information

HEF4028B

BCD to decimal decoder

Rev. 9 — 23 March 2016 Product data sheet

Table 1. Ordering information

All types operate from





C to +85



Type number Package

Name Description Version

HEF4028BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Summary of content (12 pages)

PAGE 1
HEF4028B BCD to decimal decoder Rev. 9 — 23 March 2016 Product data sheet 1. General description The HEF4028B is a 4-bit BCD to decimal decoder, a 4-bit BCO to octal decoder with active LOW enable or an 8-output (Y0 to Y7) inverting demultiplexer. The outputs are fully buffered for best performance. When used as a BCD to decimal decoder a 1-2-4-8 BCD code applied to inputs A0 to A3 causes the selected output to be HIGH. The other nine outputs will be LOW.
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HEF4028B Nexperia BCD to decimal decoder 4. Functional diagram $ $ $ $ '(&2'(5 < < < < < < < < < < DDH Fig 1. Functional diagram < < $ < < $ < < $ < < $ < < DDH Fig 2. Logic diagram HEF4028B Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 9 — 23 March 2016 © Nexperia B.V. 2017.
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HEF4028B Nexperia BCD to decimal decoder 5. Pinning information 5.1 Pinning +() % < 9'' < < < < < $ < $ < $ < $ 966 < DDH Fig 3. Pin configuration 5.2 Pin description Table 2. Pin description Symbol Pin Description Y0 to Y9 3, 14, 2, 15, 1, 6, 7, 4, 9, 5 output (active HIGH) VSS 8 ground supply voltage A0 to A3 10, 13, 12, 11 address input VDD 16 supply voltage 6.
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HEF4028B Nexperia BCD to decimal decoder Function table [1] …continued Table 3. Inputs Outputs A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 H L L H L L L L L L L L L H H L H X L L L L L L L L L L [2] H H X X L L L L L L L L L L [2] [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. [2] Extraordinary states. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
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HEF4028B Nexperia BCD to decimal decoder 9. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD.
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HEF4028B Nexperia BCD to decimal decoder Table 7. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C. Symbol Parameter tt [1] Conditions transition time VDD see Figure 4 Extrapolation formula Min Typ Max Unit 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns 5V [1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF). Table 8.
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HEF4028B Nexperia BCD to decimal decoder W: 9, QHJDWLYH SXOVH 90 90 9 9, WI WU WU WI SRVLWLYH SXOVH 90 90 9 W: DDM a. Input waveforms 9'' * 9, 92 '87 &/ 57 DDJ b. Test circuit Test data is given in Table 10. Definitions for test circuit: DUT = Device Under Test; CL = load capacitance including jig and probe capacitance; RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
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HEF4028B Nexperia BCD to decimal decoder 12.
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HEF4028B Nexperia BCD to decimal decoder 13. Abbreviations Table 11. Abbreviations Acronym Description BCD Binary Coded Decimal BCO Binary Coded Octal 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4028B v.9 20160323 Product data sheet - HEF4028B v.8 Modifications: HEF4028B v.8 Modifications: • Type number HEF4028BP (SOT38-4) removed. 20111117 • • • Product data sheet - HEF4028B v.7 Legal pages updated.
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HEF4028B Nexperia BCD to decimal decoder 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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HEF4028B Nexperia BCD to decimal decoder Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use.
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Nexperia HEF4028B BCD to decimal decoder 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . .