Data Sheet

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1. General description

The HEF4046B is a phase-locked loop circuit that consists of a linear Voltage Controlled

Oscillator (VCO) and two different phase comparators with a common signal input

amplifier and a common comparator input. A 7 V regulator (Zener) diode is provided for

supply voltage regulation if necessary. For a functional description see Section 6

It operates over a recommended V

power supply range of 3 V to 15 V referenced to V

(usually ground). Unused inputs must be connected to V

, V

, or another input.

2. Features and benefits

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 Specified from 40 C to +85 C

 Complies with JEDEC standard JESD 13-B

3. Ordering information

HEF4046B

Phase-locked loop

Rev. 6 — 24 March 2016 Product data sheet

Table 1. Ordering information

All types operate from





C to +85



Type number Package

Name Description Version

HEF4046BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Summary of content (19 pages)

PAGE 1
HEF4046B Phase-locked loop Rev. 6 — 24 March 2016 Product data sheet 1. General description The HEF4046B is a phase-locked loop circuit that consists of a linear Voltage Controlled Oscillator (VCO) and two different phase comparators with a common signal input amplifier and a common comparator input. A 7 V regulator (Zener) diode is provided for supply voltage regulation if necessary. For a functional description see Section 6.
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HEF4046B Nexperia Phase-locked loop 4. Functional diagram 3+$6( &203$5$725 6,*B,1 3& B287 &203B,1 3& B287 3+$6( &203$5$725 · 1 5 3&3 9&2B,1 9&2B287 /2: 3$66 ),/7(5 & $ & & 9&2 966 5 5 5 5 6)B287 6285&( )2//2:(5 & % 966 56) 966 ,1+ 966 SLQ =(1(5 DDH Fig 1. Functional diagram 5. Pinning information 5.
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HEF4046B Nexperia Phase-locked loop 5.2 Pin description Table 2.
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HEF4046B Nexperia Phase-locked loop the frequency range of input signals on which the PLL will lock if it was initially out of lock. The frequency lock range (2fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range.
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HEF4046B Nexperia Phase-locked loop Phase comparator 2 is an edge-controlled digital memory network. It consists of four flip-flops, control gating and a 3-state output circuit comprising p and n-type drivers with a common output node. When the p-type or n-type drivers are ON, they pull the output up to VDD or down to VSS respectively. This type of phase comparator only acts on the positive-going edges of the signals at SIG_IN and COMP_IN.
PAGE 6
HEF4046B Nexperia Phase-locked loop Figure 6 shows the state diagram for phase comparator 2. Each circle represents a state of the comparator. The number at the top, inside each circle, represents the state of the comparator, while the logic state of the signal and comparator inputs are represented by a ‘0’ for a logic LOW or a ‘1’ for a logic HIGH, and they are shown in the left and right bottom of each circle.
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HEF4046B Nexperia Phase-locked loop 7. Limiting values Table 3. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current IDD supply current Tstg storage temperature Tamb ambient temperature Conditions Max Unit 0.5 +18 V VI < 0.5 V or VI > VDD + 0.5 V - 10 0.5 VDD + 0.5 - 10 mA - 10 mA VO < 0.
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HEF4046B Nexperia Phase-locked loop 9. Static characteristics Table 5. Static characteristics VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter Conditions Tamb = 40 C VDD Min HIGH-level input voltage VIH LOW-level input voltage VIL VOH VOL IOZ OFF-state output current supply current IDD input capacitance CI Min Max 3.5 - 3.5 - 3.5 - V - 7.0 - 7.0 - V 15 V 11.0 - 11.0 - 11.0 - V 5V - 1.5 - 1.5 - 1.5 V 10 V - 3.0 - 3.0 - 3.
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HEF4046B Nexperia Phase-locked loop 10. Dynamic characteristics Table 6. Dynamic characteristics VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns. Symbol Parameter Conditions VDD Min Typ Max Unit SIG_IN input; at self-bias operating point 5V - 750 - k 10 V - 220 - k 15 V - 140 - k SIG_IN input A.C.
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HEF4046B Nexperia Phase-locked loop Table 6. Dynamic characteristics …continued VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns. Symbol Parameter Conditions f/f relative frequency variation for VCO see Figure 13 and 14  duty factor input resistance Rin VDD Min Typ Max Unit R1 > 10 k 5V - 0.50 - % Hz R1 > 400 k 10 V - 0.25 - % Hz R1 = M 15 V - 0.
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HEF4046B Nexperia Phase-locked loop 11.1 VCO component selection Recommended range for R1 and R2: 10 k to 1 M; for C1: 50 pF to any practical value. 1. VCO without frequency offset (R2 = ).  a. Given f0: use f0 with Figure 7 to determine R1 and C1. b. Given fmax: calculate f0 from f0 = 0.5fmax; use f0 with Figure 7 to determine R1 and C1. 2. VCO with frequency offset. a.
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HEF4046B Nexperia Phase-locked loop DDH 5 5 DDH 3 : IPD[ IPD[ 5 Nȍ Line (1): VDD = 5 V; R2 = ; VCO_IN at 0.5VDD; CL = 50 pF. Line (2): VDD = 10 V, 15 V. Lines (1) and (2): VDD = 15 V; Lines (3) and (4): VDD = 10 V; Lines (5) and (6): VDD = 5 V; Lines (1), (3), and (5): C1 = 50 pF; Lines (2), (4), and (6): C1 = 1 F. Fig 9.
PAGE 13
HEF4046B Nexperia Phase-locked loop I IPD[ I IR IR I ǻ9 ǻ9 9'' 9'' 99&2 ,1 DDH See Section 10. For VCO linearity: f1 + f2 f 0 = -------------2 f 0 – f 0 linearity = ----------------  100 % f 0 This figure and the above formula also apply to source follower linearity: substitute VO at SF_OUT for f. V = 0.3 V at VDD = 5 V; V = 2.5 V at VDD = 10 V; V = 5.0 V at VDD = 15 V. Fig 13.
PAGE 14
HEF4046B Nexperia Phase-locked loop DDH OLQ DDH OLQ 5 Nȍ 5 Nȍ a. VDD = 5 V b. VDD = 10 V DDH OLQ 5 Nȍ c. VDD = 15 V R2 = ; Line (1): C1 = 1 F; Line (2): C1 = 1 nF; Line (3): C1 = 100 pF; Line (4): C1 = 50 pF. Fig 14.
PAGE 15
HEF4046B Nexperia Phase-locked loop 12.
PAGE 16
HEF4046B Nexperia Phase-locked loop 13. Revision history Table 8. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4046B v.6 20160324 Product data sheet - HEF4046B v.5 Modifications: HEF4046B v.5 Modifications: • Type number HEF4046BP (SOT38-4) removed. 20111118 • • • Product data sheet - HEF4046B v.4 Section Applications removed Table 5: IOH minimum values changed to maximum Table 6: Rin typical value changed from 106 M to 10 M HEF4046B v.
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HEF4046B Nexperia Phase-locked loop 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 18
HEF4046B Nexperia Phase-locked loop Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use.
PAGE 19
Nexperia HEF4046B Phase-locked loop 16. Contents 1 2 3 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 11 11.1 12 13 14 14.1 14.2 14.3 14.4 15 16 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . .