Data Sheet

ManualsBrandsNEXPERIA ManualsLogic ICsLogic IC - Inverter Inverter 4000B SO 16

1. General description

The HEF4049B provides six inverting buffers with high current output capability suitable

for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’

supply voltage are permitted, the buffers may also be used to convert logic levels of up to

15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements

is shown in Table 3

It operates over a recommended V

power supply range of 3 V to 15 V referenced to V

(usually ground). Unused inputs must be connected to V

, V

, or another input.

2. Features and benefits

 Accepts input voltages in excess of the supply voltage

 Fully static operation

 5 V, 10 V, and 15 V parametric ratings

 Standardized symmetrical output characteristics

 Specified from 40 C to +85 C

 Complies with JEDEC standard JESD 13-B

3. Applications

 LOCMOS (Local Oxidation CMOS) to DTL/TTL converter

 HIGH sink current for driving two TTL loads

 HIGH-to-LOW level logic conversion

4. Ordering information

HEF4049B

Hex inverting buffers

Rev. 11 — 23 June 2016 Product data sheet

Table 1. Ordering information

All types operate from





C to +85



Type number Package

Name Description Version

HEF4049BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

Summary of content (12 pages)

PAGE 1
HEF4049B Hex inverting buffers Rev. 11 — 23 June 2016 Product data sheet 1. General description The HEF4049B provides six inverting buffers with high current output capability suitable for driving TTL or high capacitive loads. Since input voltages in excess of the buffers’ supply voltage are permitted, the buffers may also be used to convert logic levels of up to 15 V to standard TTL levels. Their guaranteed fan-out into common bipolar logic elements is shown in Table 3.
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HEF4049B Nexperia Hex inverting buffers 5. Functional diagram $ $ $ $ $ $ < < < < < LQSXW < < $ DDL Fig 1. Logic symbol HEF4049B Product data sheet 966 DDH PQD Fig 2. Logic diagram for one gate All information provided in this document is subject to legal disclaimers. Rev. 11 — 23 June 2016 Fig 3. Input protection circuit © Nexperia B.V. 2017.
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HEF4049B Nexperia Hex inverting buffers 6. Pinning information 6.1 Pinning +() % 9'' Q F < < $ $ < Q F $ < < $ $ < 966 $ DDH Fig 4. Pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin Description VDD 1 supply voltage 1Y to 6Y 2, 4, 6, 10, 12, 15 output 1A to 6A 3, 5, 7, 9, 11, 14 input VSS 8 ground supply voltage n.c. 13, 16 not connected 7. Functional description Table 3.
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HEF4049B Nexperia Hex inverting buffers 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD supply voltage IIK input clamping current VI input voltage IOK output clamping current II/O input/output current Conditions VI < 0.5 V Min Max Unit 0.5 +18 V 10 - 0.5 +18 V - 10 mA - 10 mA VO < 0.5 V or VO > VDD + 0.
PAGE 5
HEF4049B Nexperia Hex inverting buffers Table 6. Static characteristics …continued VSS = 0 V; VI = VSS or VDD unless otherwise specified. Symbol Parameter VOH Conditions HIGH-level output voltage LOW-level output voltage VOL HIGH-level output current IOH LOW-level output current IOL IO < 1 A Tamb = 40 C VDD 5V IO < 1 A Tamb = 25 C Tamb = 85 C Min Max Min Max Min Max 4.95 - 4.95 - 4.95 - Unit V 10 V 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.
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HEF4049B Nexperia Hex inverting buffers Table 8. Dynamic power dissipation PD PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C.
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HEF4049B Nexperia Hex inverting buffers 9'' * 9, 92 '87 57 &/ DDJ Test data is given in Table 10. Definitions for test circuit: CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. Fig 6. Test circuit for measuring switching times Table 10. Test data Supply voltage Input VDD VI VM tr, tf CL 5 V to 15 V VDD 0.
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HEF4049B Nexperia Hex inverting buffers 13.
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HEF4049B Nexperia Hex inverting buffers 14. Abbreviations Table 11. Abbreviations Acronym Description DTL Diode Transistor Logic DUT Device Under Test LOCMOS Local Oxidation CMOS TTL Transistor-Transistor Logic 15. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4049B v.11 20160623 Product data sheet - HEF4049B v.10 Modifications: HEF4049B v.10 Modifications: HEF4049B v.
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HEF4049B Nexperia Hex inverting buffers 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
PAGE 11
HEF4049B Nexperia Hex inverting buffers Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use.
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Nexperia HEF4049B Hex inverting buffers 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 © General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . .