Computer Hardware User Manual

DDR3THIN-MN-XXX 51 Doc. Rev. 1.11
Group
Name
Signal
Name
TLA
Input
Group
Name
Signal
Name
TLA
Input
DataByte7_
1
1_DQ63 S2_A0:0 DataByte3_
1
1_DQ31 S2_D2:6
1_DQ62 S2_A0:1 1_DQ30 S2_D2:3
1_DQ61 S2_A0:5 1_DQ29 S2_E2:0
1_DQ60 S2_CK1 1_DQ28 S2_E2:1
1_DQ59 S2_A0:2 1_DQ27 S2_D2:4
1_DQ58 S2_A0:3 1_DQ26 S2_D2:1
1_DQ57 S2_A0:7 1_DQ25 S2_E2:2
1_DQ56 S2_A1:0 1_DQ24 S2_E2:3
DataByte6_
1
1_DQ55 S2_A1:2 DataByte2_
1
1_DQ23 S2_E2:4
1_DQ54 S2_A1:3 1_DQ22 S2_E2:5
1_DQ53 S2_A1:7 1_DQ21 S2_E3:2
1_DQ52 S2_D1:5 1_DQ20 S2_E3:3
1_DQ51 S2_A1:1 1_DQ19 S2_E2:6
1_DQ50 S2_A1:4 1_DQ18 S2_E2:7
1_DQ49 S2_D1:7 1_DQ17 S2_E3:1
1_DQ48 S2_D1:6 1_DQ16 S2_E3:4
DataByte5_
1
1_DQ47 S2_D1:4 DataByte1_
1
1_DQ15 S2_E3:6
1_DQ46 S2_D1:1 1_DQ14 S2_E3:7
1_DQ45 S2_D0:7 1_DQ13 S2_E1:4
1_DQ44 S2_D0:6 1_DQ12 S2_E1:1
1_DQ43 S2_D1:3 1_DQ11 S2_E3:5
1_DQ42 S2_D1:2 1_DQ10 S2_E1:7
1_DQ41 S2_D0:5 1_DQ9 S2_E1:3
1_DQ40 S2_D0:4 1_DQ8 S2_E1:2
DataByte4_
1
1_DQ39 S2_D0:3 DataByte0_
1
1_DQ7 S2_E1:0
1_DQ38 S2_D0:2 1_DQ6 S2_E0:7
1_DQ37 S2_C2:1 1_DQ5 S2_E0:3
1_DQ36 S2_C2:4 1_DQ4 S2_E0:2
1_DQ35 S2_D0:1 1_DQ3 S2_Q2
1_DQ34 S2_D0:0 1_DQ2 S2_E0:5
1_DQ33 S2_C2:6 1_DQ1 S2_E0:1
1_DQ32 S2_C2:7 1_DQ0 S2_E0:0
Table 5 – B_DDR3D_3A TLA MagniVu Channel Grouping (cont’d.)
Notes:
1. The ‘S’ in front of a TLA channel denotes the Slave card of the merged pair
2. The ‘M’ in front of a TLA channel denotes the Master card of the merged pair