Computer Hardware User Manual

DDR3THIN-MN-XXX 55 Doc. Rev. 1.11

The B_DDR3D_XX supports acquire two samples of valid Write data on each rising edge of the

DDR3 clock. So to acquire both pieces of data the WrA_DatHi/Lo data groups must have their

sample point set to that shown by Sample Pt. #1 in the Figure, and the WrB_DatHi/Lo data

groups must have their sample point set to that shown by Sample Pt. #2.

NOTE - It is important to note that because of the design of the TLA acquisition card inputs and

the Strobe activity prior to Write data being placed on the data bus it will appear as if the Strobes

indicate valid Write data earlier than the data is actually there (see the circle indicated as Write

Data Preamble in Figure 5). These Write Preamble Strobe edges should NOT be used to

determine where valid Write data is on the data bus.

5.7 B_DDR3D_XX Support Setup

Using the B_DDR3D_XX supports it is possible to acquire both Read and Write data by setting

the sample point of the data groups appropriately. To adjust the Read Data group sample points

first make an appropriate acquisition of Read data by triggering on a Read command. Then

create a timing window display of MagniVu data and display the Data_Hi and Data_Lo 32-bit

data groups, the individual Command group signals and the DDR3 clock that was used for the

data acquisition (DDRCK0). A sample waveform display of MagniVu Read data is shown in

Figure 6. To determine the sample point, locate the smallest window of valid Read data during

the acquired burst (see Figure 6). Note that in this instance the first piece of valid data happens

significantly after the rising edge it is associated with. In fact the initial valid data appears at the

DDR Clock falling edge. This delay must be taken into account or data will not be aligned

properly in the Listing display window. Note that A and B data (corresponding to ADataHi/Lo

and BDataHi/Lo data groups) have been indicated.

Figure 6 - Locating Minimum Valid B_DDR3D_XX Read Data Window

Read Command

Valid Read

Data Begins

Minimum

S&H

Latency

expires

A B A