Block Diagram of System/RF Blocks Original 11/97 System Module UP8T NSE–3 3/A3–1
Circuit Diagram of Baseband Original 11/97 System Module UP8T NSE–3 (Version 12 Edit 8) for layout version 14 3/A3–2
Circuit Diagram of Power Supply (Version 14 Original 11/97 System Module UP8T NSE–3 Edit 41) for layout version 14 3/A3–3
Circuit Diagram of SIM Connectors (Version 14 Original 11/97 System Module UP8T NSE–3 Edit 9) for layout version 14 3/A3–4
Circuit Diagram of CPU Block (Version 14 System Module UP8T NSE–3 Edit 23) for layout version 14 NSE–3 (NSE–1) Original 11/97 3/A3–5
Circuit Diagram of Audio Original 11/97 System Module UP8T NSE–3 (Version 14 Edit 27) for layout version 14 3/A3–6
Circuit Diagram of IR Module (Version 14 Original 11/97 System Module UP8T NSE–3 Edit 21) for layout version 14 3/A3–7
Circuit Diagram of RF Block (Version Original 11/97 System Module UP8T NSE–3 14 Edit 26) for layout version 14 3/A3–8
System Module UP8T Layout Diagram of UPT8T – Top (Version 14) testpoint name condition dc–level J102 FBUS_RX power on pulsed DC (0V/2.8V) J103 MBUS power on pulsed DC (0V/2.8V) J107 LGND J110 VPP flash programming nominal 5V (5V flash) or 3.0V (3V flash) J111 WDDISX power on reset state 0V, normal state 2.
System Module UP8T Layout Diagram of UPT8T – Bottom (Version 14) testpoint name condition dc–level J101 FBUS_TX active state pulsed DC (0V72.8V) J104 CCONTCSX (CCONT chip select) active state pulse active 0V, non–active 2.8V J108 CHRG_CTRL charger connected pulsed DC (0V/2.8V) J220 V5V active state nominal 5.0V (min 4.8V, max 5.2V) J223 CCONTINT (charger, RTC interrupt) interrupt pulse active 2.8V, non–active 0V J224 VCOBBA active state nominal 2.8V (min 2.7V, max 2.
