User's Manual
Table Of Contents
- 1 Introduction
- 2 Module Power
- 3 Physical Interfaces
- Module Mounting to Host Board (Reference)
- Connectors
- Connectors
- I/O Connector Pin Assignments
- Circuit Protection
- Antenna
- Control Connector Signal Functions
- Module Power (Pins 85, 87, 89, 91, 93, 95, 97, 99)
- Power Control (Pin 35) - (PWR_CTL)
- Level Translation Reference Power (Pin 77)
- USB (Pins 1, 3, 5, 7, 9)
- General Purpose Input/Output Interface
- RTC Sleep
- Serial Interfaces & Handshake (Pins 11, 13, 15, 17, 19, 21, 23, 25)
- Multi-Channel Serial Interface (MCSI) – (Pins 12, 14, 16, 18)
- VBackup Input (Pin83)
- Using VBackup
- Analog-to-Digital Input (Pin 74)
- Handset Microphone Input (Pins 65, 67)
- Handset Microphone Bias Output (Pin 63)
- Handset Speaker Output (Pins 71, 73)
- Headset Microphone Input (Pin 55)
- Headset Microphone Bias Output (Pin 53)
- Headset Speaker Output Left & Right (Pins 57, 59)
- Headset Output Common Mode (Pin 61)
- Headset Detect (Pin 47)
- Subscriber Identity Module (SIM) Carrier (Pins 76, 78, 80, 82, 84)
- 4 Hardware Design
- General Design Guidelines for Using Novatel Wireless M2M GSM Modules
- Enabling the Transmission Modes for the GSM/GPRS Services
- Voice Communication
- Circuit-Switched Data
- SMS: Short Message Services
- Provisioning The SIM
- GSM Services Supported by the Novatel Wireless M2M Enabler IIIG Module
- GPRS Services Supported by the Novatel Wireless M2M Enabler IIIG Module
- Selecting the GSM Modes of Operation
- 5 Setup and Initialization
- 6 Integration and Testing
50 novatelwireless.com
Figure 4-4 Example of Vbat Voltage Droop
If the Vbat drops too low, the Enabler modules will reset. To minimize the trace loss, it is
suggested to use a larger trace that spans several pins as shown in Figure 5. Any concern
about solderability can be mitigated by using solder mask with cutouts for the individual pins
as shown by the blue lines in the figure. The layout should provide sufficient trace width over
the entire trace from the Enable modules all the way to the source of the Vbat voltage. Any
transitions between layers for this trace should utilize multiple vias.
Since even the best layout will have some impedance from the source to the Enabler module,
sufficient bulk decoupling capacitance is required at the Vbat input to the Enabler module. It
is suggested to use at least two 1000 uF, low ESR, tantalum capacitors located very close to
the Enabler interface connector Vbat pins. Any thermal relief used on these capacitors should
comply with the information given above in order to provide the lowest impedance possible.
The grounding of these capacitors is critical. Therefore, it should be a low impedance and
should utilize multiple vias to the internal ground plane close to the capacitor as well.