Integration Guide
Table Of Contents
- 1 Safety Precautions
- 2 Manual Overview
- 2.1 REFERENCES
- 2.1.1 ENFORA ENABLER III LPP PRODUCT DOCUMENTATION MANUALS
- 2.1.2 GSM DEVICE SPECIFICATIONS
- 2.1.3 FEDERAL COMMUNICATIONS COMMISSION (FCC)
- 2.1.4 FCC OFFICE OF ENGINEERING AND TECHNOLOGY (OET)
- 2.1.5 INDUSTRY CANADA
- 2.1.6 ENVIRONMENTAL REGULATIONS
- 2.1.7 MECHANICAL SPECIFICATIONS
- 2.1.8 RF AND EMI SPECIFICATIONS
- 2.1 REFERENCES
- 3 Introduction
- 4 Technical Specifications
- 5 Physical Interfaces
- 5.1 MODULE MOUNTING TO HOST BOARD (REFERENCE)
- 5.2 I/O PIN ASSIGNMENTS
- 5.3 CIRCUIT PROTECTION
- 5.4 CONTROL CONNECTOR SIGNAL DESCRIPTIONS AND FUNCTIONS
- 5.4.1 MODULE POWER (PINS 30, 31)
- 5.4.2 ON/OFF SIGNAL (PIN 4)
- 5.4.3 ON/OFF STATUS (PIN 5)
- 5.4.4 GENERAL PURPOSE INPUT SIGNALS (PINS 10, 11)
- 5.4.5 GENERAL PURPOSE OUTPUT SIGNALS (PINS 12, 13)
- 5.4.6 RESET SIGNAL (PIN 24)
- 5.4.7 USB (PINS 34, 35, 36)
- 5.4.8 SERIAL INTERFACES
- 5.4.9 HANDSET MICROPHONE INPUT (PINS 37, 38)
- 5.4.10 HANDSET SPEAKER OUTPUT (PINS 39, 40)
- 5.5 SUBSCRIBER IDENTITY MODULE (SIM) (PINS 42, 43, 44, 45, 46)
- 5.6 ANTENNA
- 6 GPS Performance
- 7 GSM/GPRS Modes of Operation
- 8 Software Interface
- 9 APPENDIX A - LIMITED WARRANTY
- 10 APPENDIX B - Regulatory Compliance
- 11 APPENDIX C - Glossary and Acronyms
- 12 APPENDIX E - Contacting Enfora
Enfora Enabler III LPP
Integration Guide Page 13 Revision: 0.00
The RF cable going between the Enable module and the antenna is very lossy,
therefore, the length of this cable should be kept as short as possible.
3.5.1.4 VBAT INPUT
The Enabler Vbat input can have a relative high current draw that can fluctuate
rapidly, especially when transmitting at max power and burst mode. The Vbat
interface must be designed to provide the required instantaneous voltage and
current with minimal voltage droop. This includes both sufficient bulk decoupling
capacitance as well as adequate layout provisions.
Similar to the discussion on thermal relief, the use of narrow traces to connect the
Vbat pins to the source voltage can act like a high impedance and cause a
significant voltage droop when higher currents are required as shown in Figure 4. If
the Vbat drops too low, the Enabler modules will reset. To minimize the trace loss,
it is suggested to use a larger trace that spans several pins. The layout should
provide sufficient trace width over the entire trace from the Enabler module all the
way to the source of the Vbat voltage. Any transitions between layers for this trace
should utilize multiple vias.
Figure 4 - Example of Vbat Voltage Droop
Two 470 uF, low ESR, tantalum capacitors are included in the design to provide
decoupling of Vbat input voltage. Bulk decoupling capacitance is not required at
the Vbat input external to the Enabler module.