Datasheet

ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 29 - Revision 1.42
6.4.2 ISD5100 Series Analog Structure (left half) Description
IN PUT
AGC AMP
SUM 1
Σ
2 (S1M1,S1M0)
SOURCE
MUX
SUM 1 SUM MING
AM P
AUX IN AMP
FI LTO
SUM1
MUX
AN A IN A M P
AR RA Y
2 (S1S1,S1S0)
(INS0 )
1 5 14 1 3 12 1 1 10 9 8 7 6 5 4 3 2 1 0
AIG1
A I G 0 A I PD AX G 1 A XG 0 A XPD
INS0
AOS2 AOS1AOS0AOPD OPS1 OPS0 O PA1 OPA 0 V LPD
CFG0
1 5 14 1 3 12 1 1 10 9 8 7 6 5 4 3 2 1 0
VLS1 VL S0 V O L 2 VO L1 V O L 0
S1 S1 S1S0S1M1S1M0
S2 M 1 S 2 M 0 FLS0 FLD 1 F LD 0 FLPD AGPD
CFG1
INP
INSO Source
0 AGC AMP
1 AUX IN AMP
S1M1 S1M0 SOURCE
0 0 BOTH
0 1 SUM1 MUX ONLY
1 0 INP Only
1 1 Power Down
S1S1 S1S0 SOURCE
0 0 ANA IN
0 1 ARRAY
1 0 FILTO
1 1 N/C