Datasheet

ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 30 - Revision 1.42
6.4.3 ISD5100 Series Aanalog Structure (right half) Description
SUM 1
SUM2
Σ
2 (S2M1,S2M0)
FI LTER
MUX
SUM2 SUM MI NG
AM P
ARRAY
2
FI LTO
LO W PASS
FILTER
I N TE RN AL
CLOCK
MULTILEVEL
STO RA G E
ARRAY
1
(FLS0)
1
(FLPD)
ARRAY
ANA IN AM P
XCLK
(FLD 1,FLD0)
15141312111098 76 54 32 10
VLS1
VLS0 VO L2 V O L 1 VO L0 S1 S1 S1 S0 S1 M 1 S1 M 0
S2 M 1 S2 M 0 FLS0 FLD1 FLD0 FLPD
AGPD
CFG1
FLS0 SOURCE
0 SUM1
1 ARRAY
FLPD CONDITION
0 Power Up
1 Power Down
S2M1 S2M0 SOURCE
0 0 BOTH
0 1 ANA IN ONLY
1 0 FILTO ONLY
1 1 Power Down
FLD1 FLD0 SAMPLE
RATE
FILTER
BANDWIDTH
0 0 8 KHz 3.6 KHz
0 1 6.4 KHz 2.9 KHz
1 0 5.3 KHz 2.4 KHz
1 1 4.0 KHz 1.8 KHz
FILTER
MUX
FILTO