Datasheet

ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 48 - Revision 1.42
6.6. PIN DETAILS
6.6.1 Digital I/O Pins
SCL (Serial Clock Line)
The Serial Clock Line is a bi-directional clock line. It is an open-drain line requiring a pull-up resistor
to Vcc. It is driven by the "master" chips in a system and controls the timing of the data exchanged
over the Serial Data Line.
SDA (Serial Data Line)
The Serial Data Line carries the data between devices on the I
2
C interface. Data must be valid on
this line when the SCL is HIGH. State changes can only take place when the SCL is LOW. This is
a bi-directional line requiring a pull-up resistor to Vcc.
RAC (Row Address Clock)
RAC is an open drain output pin that normally marks the end of a row. At the 8 kHz sample frequency,
the duration of this period is 256 ms. RAC stays HIGH for 248 ms and stays LOW for the remaining 8
ms before it reaches the end of a row. There are 2048 rows of memory in the ISD5116 devices, 1024
rows in the ISD5108, 512 rows in the ISD5104 and 256 rows in the ISD5102.
1 ROW
RAC Waveform
During 8 KHz Operation
256 msec
T
RAC
8 msec
T
RACL
The RAC pin remains HIGH for 500 µsec and stays LOW for 15.6 µsec under the Message Cueing
mode. See the
Timing Parameters table on page 64 for RAC timing information at other sample
rates. When a record command is first initiated, the RAC pin remains HIGH for an extra T
RACML
period,
to load sample and hold circuits internal to the device. The RAC pin can be used for message
management techniques.
1 ROW
RAC Waveform
During Message Cueing
@ 8KHz Operation
500 usec
T
RACM
15.6 us
T
RACML