Datasheet

ISD5100 SERIES
Publication Release Date: Oct 31, 2008
- 6 - Revision 1.42
3. BLOCK DIAGRAM
ISD5100-Series Block Diagram
AUX IN
AMP
1.0 / 1.4 / 2.0 / 2.8
AGC
SUM1 MUX
Vol MUX
Filter
MUX
Low Pass
Filter
SUM1
FTHRU
INP
ANA OUT MUX
VOL
SUM2
ANA IN
VOL
SP+
SP-
SPEAKER
AUX OUT
ANA OUT-
ANA OUT+
MIC+
MIC -
AGCCAP
MICROPHONE
AUX IN
XCLK
ANA IN
V
SSA
V
CCA
V
SSA
V
SSD
V
SSD
V
CCD
V
CCD
64-bit/samp.
ARRAY OUTPUT MUX
ARRAY
INPUT
MUX
Input Source MUX
Array I/O Mux
FILTO
SUM1
INP
ANA IN
SUM2
FILTO
SUM2
SUM1
Summing
AMP
ANA IN
AMP
0.625/0.883/1.25/1.76
6dB
SUM2
Summing
AMP
Output MUX
Volume
Control
MIC IN
AUX IN
FILTO
ANA IN
SUM1
ANA IN
FILTO
SUM2
(ANALOG)
ARRAY
INP
SUM1 MUX
CTRL
(DIGITAL)
64-bit/samp.
ARRAY OUT
(ANALOG)
ARRAY OUT
(DIGITAL)
ARRAY
Spkr
.
AMP
AUX
OUT
AMP
Power Conditioning
RACINTSDA
SCL
A1
A0
Device Control
Internal
Clock
Multilevel/Digital
Storage Array
ANA
OUT
AMP
Σ
Σ
2
( )
VLS0
VLS1
2
( )
AIG0
AIG1
2 ( )
AXG0
AXG1
2
( )
S1S0
S1S1
2
( )
S1M0
S1M1
2
( )
S2M0
S2M1
( )
OPA0
OPA1
2
( )
OPS0
OPS1
2
( )
FLD0
FLD1
2
(INS0)
1
1
(AXPD)
1
(AGPD)
1
(FLPD)
1
(FLS0)
1
(AIPD)
1
(AOPD)
( )
3
AOS0
AOS1
AOS2
3
( )
VOL0
VOL1
VOL2
1
(V
LPD
)