User's Guide
Table Of Contents
- 1. Introduction
- 2. Specifications
- 3. Pin Configurations
- 4. Electrical Characteristics
- Appendix A Additional Information
- A.1 Outline Drawing
- A.2 Module PCB Footprint
- A.3 Optimal PCB placement of the JN5168-001-M00 Module
- A.4 JN5168-001-M00 Antenna Radiation Pattern
- A.5 Manufacturing
- A.5.1 Reflow Profile
- A.5.2 Soldering Paste and Cleaning
- A.6 Ordering Information
- A.7 Related Documents
- A.8 Federal Communication Commission Interference Statement
- A.8.1 Antennas approved by FCC for use with JN5168 modules
- A.8.2 High Power Module usage limitation
- A.8.3 FCC End Product Labelling
- A.9 Industry Canada Statement
- A.9.1 Industry Canada End Product Labelling
- A.10 European R & TTE Directive 1999/5/EC Statement
- A.11 RoHS Compliance
- A.12 Status Information
- A.13 Disclaimers
- Version Control
© NXP Laboratories UK 2012 JN-DS-JN5168-001-Myy 1v0 7
3.1. Pin Assignment
Pin
No
Pin Functions
Signal
Type
Description
Primary
Alternate Functions
1
ADC1
3.3V
Analogue to Digital Input
2 SPICLK PWM2 CMOS
SPI Master Clock Output or PWM2
Output
3
SPIMISO
CMOS
SPI Master In Slave Out Input
4 SPIMOSI PWM3 CMOS
SPI Master In Slave Out Input or
PWM3 Output
5
SPISEL0
CMSO
SPI Select From Module – SS0
Output
6
DIO0
SPISEL1
ADC3
CMOS
DIO0, SPI Master Select Output 1
or ADC input 3
7
DIO1
SPISEL2
ADC4
PC0
CMOS
DIO1, SPI Master Select Output 2,
ADC input 4 or Pulse Counter 0
Input
8
DIO2*
RFRX
TIM0CK_GT
CMOS
DIO2, Radio Receive Control
Output or Timer0 Clock/Gate Input
9
DIO3*
RFTX
TIM0CAP
CMOS
DIO3, Radio Transmit Control
Output or Timer0 Capture Input
10 DIO4 CTS0 JTAG_TCK TIM0OUT PC0 CMOS
DIO4, UART 0 Clear To Send
Input, JTAG CLK Input, Timer0
PWM Output, or Pulse Counter 0
input
11
DIO5
RTS0
JTAG_TMS
PWM1
PC1
CMOS
DIO5, UART 0 Request To Send
Output, JTAG Mode Select Input,
PWM1 Output or Pulse Counter 1
Input
12
DIO6 TXD0 JTAG_TDO PWM2
CMOS
DIO6, UART 0 Transmit Data
Output, JTAG Data Output or
PWM2 Output
13 DIO7 RXD0 JTAG_TDI PWM3 CMOS
DIO7, UART 0 Receive Data
Input, JTAG Data Input or PWM 3
Output
14
DIO8 TIM0CK_GT PC1 PWM4
CMOS
DIO8, Timer0 Clock/Gate Input,
Pulse Counter1 Input or PWM 4
Output
15 DIO9 TIM0CAP 32KXTALIN
RXD1 32KIN
CMOS
DIO9, Timer0 Capture Input, 32K
External Crystal Input, UART 1
Receive Data Input or 32K
external clock Input
16
DIO10
TIM0OUT
32KXTALOUT
CMOS
DIO10, Timer0 PWM Output or
32K External Crystal Output
17
VDD
3.3V
Supply Voltage
18
GND
0V
Digital Ground
19
DIO11 PWM1 TXD1
CMOS
DIO11, PWM1 Output or UART 1
Transmit Data Output
20
DIO12 PWM2 CTS0 JTAG_TCK ADO or
SPISMOSI
CMOS
DIO12, PWM2 Output, UART 0
Clear To Send Input, JTAG CLK
Input, Antenna Diversity Odd
Output or SPI Slave Master Out
Slave In Input
21
DIO13 PWM3 RTS0 JTAG_TMS ADE or
SPISMISO
CMOS
DIO13, PWM3 Output, UART 0
Request To Send Output, JTAG
Mode Select Input, Antenna
Diversity Even output or SPI Slave
Master In Slave Out Output
22
RESETN
CMOS
Reset input
23
DIO14
SIF_CLK
TXD0 TXD1
JTAG_TDO
SPISEL1 or
CMOS
DIO14, Serial Interface Clock,