Datasheet

74ABT125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 3 of 16
NXP Semiconductors
74ABT125
Quad buffer; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability.
[3] SO14 packages: above 70 C P
tot
derate linearly with 8 mW/K
SSOP14 and TSSOP20 packages: above 60 C P
tot
derate linearly with 5.5 mW/K
DHVQFN14 packages: above 60 C P
tot
derate linearly with 4.5 mW/K
Table 2. Pin description
Symbol Pin Description
1OE
to 4OE 1, 4, 10, 13 output enable input (active LOW)
1A to 4A 2, 5, 9, 12 data input
1Y to 4Y 3, 6, 8, 11 data output
GND 7 ground (0 V)
V
CC
14 supply voltage
Table 3. Function selection
[1]
Inputs Output
nOE nA nY
LLL
LHH
HXZ
Table 4. Limiting values
[1]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
CC
supply voltage 0.5 +7.0 V
V
I
input voltage 1.2 +7.0 V
V
O
output voltage output in OFF-state or HIGH-state 0.5 +5.5 V
I
IK
input clamping current V
I
< 0 V 18 - mA
I
OK
output clamping current V
O
< 0 V 50 - mA
I
O
output current output in LOW-state - 128 mA
T
j
junction temperature
[2]
-150C
T
stg
storage temperature 65 +150 C
P
tot
total power dissipation T
amb
= 40 C to +85 C
[3]
-500mW