Datasheet

74ABT125 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 6 — 3 November 2011 5 of 16
NXP Semiconductors
74ABT125
Quad buffer; 3-state
[1] This parameter is valid for any V
CC
between 0 V and 2.1 V, with a transition time of up to 10 ms. From V
CC
= 2.1 V to V
CC
= 5 V  10 %,
a transition time of up to 100 s is permitted.
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[3] This is the increase in supply current for each input at 3.4 V.
10. Dynamic characteristics
I
CC
additional supply
current
per control pin; V
CC
= 5.5 V;
one control input at 3.4 V, other
inputs at V
CC
or GND
[3]
outputs enabled - 0.5 1.5 - 1.5 mA
outputs disabled - 50 250 - 250 mA
one enable input at 3.4 V and other
inputs at V
CC
or GND; outputs
disabled
- 0.5 1.5 - 1.5 mA
C
I
input capacitance V
I
= 0 V or V
CC
-4- - -pF
C
O
output capacitance outputs disabled; V
O
=0V orV
CC
-7- - -pF
Table 6. Static characteristics
…continued
Symbol Parameter Conditions 25 C 40 C to +85 C Unit
Min Typ Max Min Max
Table 7. Dynamic characteristics
GND = 0 V. Test circuit is shown in Figure 8
.
Symbol Parameter Conditions 25 C; V
CC
= 5.0 V 40 C to +85 C;
V
CC
= 5.0 V  0.5 V
Unit
Min Typ Max Min Max
t
PLH
LOW to HIGH
propagation delay
nA to nY, see Figure 6 1.0 2.8 4.1 1.0 4.6 ns
t
PHL
HIGH to LOW
propagation delay
nA to nY; see Figure 6 1.0 3.1 4.6 1.0 4.9 ns
t
PZH
OFF-state to HIGH
propagation delay
nOE to nY; see Figure 7 1.0 3.2 5.0 1.0 5.9 ns
t
PZL
OFF-state to LOW
propagation delay
nOE to nY; see Figure 7 1.0 4.2 6.2 1.0 6.8 ns
t
PHZ
HIGH to OFF-state
propagation delay
nOE to nY; see Figure 7 1.0 4.1 5.4 1.0 6.2 ns
t
PLZ
LOW to OFF-state
propagation delay
nOE to nY; see Figure 7 1.5 2.8 5.0 1.5 5.5 ns