Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74AHC SO 14

1. General description

The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC

standard No. JESD7-A.

The 74AHC00; 74AHCT00 provides the quad 2-input NAND function.

2. Features

n Balanced propagation delays

n All inputs have Schmitt-trigger actions

n Inputs accept voltages higher than V

n Input levels:

u For 74AHC00: CMOS level

u For 74AHCT00: TTL level

n ESD protection:

u HBM EIA/JESD22-A114E exceeds 2000 V

u MM EIA/JESD22-A115-A exceeds 200 V

u CDM EIA/JESD22-C101C exceeds 1000 V

n Multiple package options

n Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

74AHC00; 74AHCT00

Quad 2-input NAND gate

Rev. 04 — 28 April 2008 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC00

74AHC00D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74AHC00PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74AHC00BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

Summary of content (14 pages)

PAGE 1
74AHC00; 74AHCT00 Quad 2-input NAND gate Rev. 04 — 28 April 2008 Product data sheet 1. General description The 74AHC00; 74AHCT00 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. JESD7-A. The 74AHC00; 74AHCT00 provides the quad 2-input NAND function. 2.
PAGE 2
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate Table 1. Ordering information …continued Type number Package Temperature range Name Description Version 74AHCT00D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHCT00PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
PAGE 3
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A 1 data input 1B 2 data input 1Y 3 data output 2A 4 data input 2B 5 data input 2Y 6 data output GND 7 ground (0 V) 3Y 8 data output 3A 9 data input 3B 10 data input 4Y 11 data output 4A 12 data input 4B 13 data input VCC 14 supply voltage 6. Functional description Table 3.
PAGE 4
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage IIK input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to (VCC + 0.5 V) Min Max Unit −0.5 +7.0 V −0.5 +7.
PAGE 5
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions Min −40 °C to +85 °C −40 °C to +125 °C Unit Typ Max Min Max Min Max 74AHC00 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.
PAGE 6
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions Min −40 °C to +85 °C −40 °C to +125 °C Unit Typ Max Min Max Min Max ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.0 - 20 - 40 µA ∆ICC additional supply current per input pin; VI = VCC − 2.1 V; other pins at VCC or GND; IO = 0 A; VCC = 4.5 V to 5.
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4AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate 11. Waveforms VI VM nA, nB input GND tPLH tPHL VOH VM nY output VOL 001aah088 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Input to output propagation delays Table 8. Measurement points Type Input Output VM VM 74AHC00 0.5 × VCC 0.5 × VCC 74AHCT00 1.5 V 0.
PAGE 8
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate Table 9. Test data Type Input Load Test VI tr, tf CL 74AHC00 VCC ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL 74AHCT00 3.0 V ≤ 3.0 ns 15 pF, 50 pF tPLH, tPHL 74AHC_AHCT00_4 Product data sheet © NXP B.V. 2008. All rights reserved. Rev.
PAGE 9
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.
PAGE 10
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.
PAGE 11
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.18 mm c D (1) Dh E (1) Eh 0.2 3.
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74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charge Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11.
PAGE 13
74AHC00; 74AHCT00 NXP Semiconductors Quad 2-input NAND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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NXP Semiconductors 74AHC00; 74AHCT00 Quad 2-input NAND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . .