Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate OR gate 74AHC TSSOP 14

1. General description

The 74AHC32; 74AHCT32 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with JEDEC standard

No. 7-A.

The 74AHC32; 74AHCT32 provides the 2-input OR function.

2. Features

n Balanced propagation delays

n All inputs have Schmitt-trigger actions

n Inputs accept voltages higher than V

n Input levels:

u For 74AHC32: CMOS level

u For 74AHCT32: TTL level

n ESD protection:

u HBM EIA/JESD22-A114E exceeds 2000 V

u MM EIA/JESD22-A115-A exceeds 200 V

u CDM EIA/JESD22-C101C exceeds 1000 V

n Multiple package options

n Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

74AHC32; 74AHCT32

Quad 2-input OR gate

Rev. 04 — 22 May 2008 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC32

74AHC32D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74AHC32PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74AHC32BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

Summary of content (14 pages)

PAGE 1
74AHC32; 74AHCT32 Quad 2-input OR gate Rev. 04 — 22 May 2008 Product data sheet 1. General description The 74AHC32; 74AHCT32 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC32; 74AHCT32 provides the 2-input OR function. 2.
PAGE 2
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate Table 1. Ordering information …continued Type number Package Temperature range Name Description Version 74AHCT32D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHCT32PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
PAGE 3
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate 5. Pinning information 1A terminal 1 index area 14 VCC 5.1 Pinning 1 14 VCC 1B 2 13 4B 1B 2 13 4B 12 4A 1Y 3 12 4A 2A 4 32 11 4Y 2B 5 GND(1) 10 3B 2Y 6 1 1A 2B 5 2Y 6 9 3A GND 7 8 3Y 32 11 4Y 10 3B 9 8 4 3Y 2A 7 3 GND 1Y 3A 001aad102 Transparent top view 001aad101 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
PAGE 4
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate 6. Functional description Function table[1] Table 3. Input Output nA nB nY L L L X H H H X H [1] H = HIGH voltage level; L = LOW voltage level; X = don’t care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage IIK input clamping current VI < −0.
PAGE 5
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate Table 5. Operating conditions …continued Symbol Parameter Conditions Min Typ Max Unit 74AHCT32 VCC supply voltage 4.5 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate - - 20 ns/V VCC = 4.5 V to 5.5 V 9. Static characteristics Table 6.
PAGE 6
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max 74AHCT32 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - - 0.8 - 0.8 - 0.
PAGE 7
4AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max - 3.1 6.9 1.0 8.0 1.0 9.0 ns - 4.3 7.9 1.0 9.0 1.0 10.0 ns - 12 - - - - - pF 74AHCT32; VCC = 4.5 V to 5.
PAGE 8
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate VI negative pulse tW 90 % VM VM 10 % GND tr tf tr VI positive pulse GND tf 90 % VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Load circuitry for measuring switching times Table 9.
PAGE 9
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.
PAGE 10
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.
PAGE 11
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.18 c D (1) Dh E (1) Eh 0.2 3.1 2.
PAGE 12
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model 14. Revision history Table 11.
PAGE 13
74AHC32; 74AHCT32 NXP Semiconductors Quad 2-input OR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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NXP Semiconductors 74AHC32; 74AHCT32 Quad 2-input OR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . .