Datasheet

74AHC_AHCT573 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 7 — 8 November 2011 9 of 19
NXP Semiconductors
74AHC573; 74AHCT573
Octal D-type transparant latch; 3-state
[1] Typical values are measured at nominal supply voltage (V
CC
= 3.3 V and V
CC
= 5.0 V).
[2] t
pd
is the same as t
PHL
and t
PLH
.
[3] t
en
is the same as t
PZH
and t
PZL
.
[4] t
dis
is the same as t
PHZ
and t
PLZ
.
[5] C
PD
is used to determine the dynamic power dissipation (P
D
in W).
P
D
=C
PD
 V
CC
2
 f
i
 N+(C
L
 V
CC
2
 f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
 V
CC
2
 f
o
) = sum of the outputs.
t
h
hold time Dn to LE; see Figure 10
V
CC
= 3.0 V to 3.6 V 1.5 - - 1.5 - 1.5 - ns
V
CC
= 4.5 V to 5.5 V 1.5 - - 1.5 - 1.5 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz;
V
I
=GNDtoV
CC
[5]
-12- - - - -pF
74AHCT573; V
CC
= 4.5 V to 5.5 V
t
pd
propagation
delay
Dn to Qn; see Figure 7
[2]
C
L
= 15 pF - 3.5 5.5 1 6.5 1 7.0 ns
C
L
= 50 pF - 4.9 7.5 1 8.5 1 9.5 ns
LE to Qn; see Figure 8
[2]
C
L
= 15 pF - 3.9 6.0 1 7.0 1 7.5 ns
C
L
= 50 pF - 5.5 8.5 1 9.5 1 11.0 ns
t
en
enable time OE to Qn; see Figure 9
[3]
C
L
= 15 pF - 4.1 6.5 1 7.5 1 8.5 ns
C
L
= 50 pF - 5.9 8.5 1 10.0 1 11.0 ns
t
dis
disable time OE to Qn; see Figure 9
[4]
C
L
= 15 pF - 4.5 6.5 1 7.5 1 8.5 ns
C
L
= 50 pF - 6.4 9.0 1 10.0 1 11.5 ns
t
W
pulse width LE HIGH; see Figure 8 5.0 - - 5.0 - 5.0 - ns
t
su
set-up time Dn to LE; see Figure 10 3.5 - - 3.5 - 3.5 - ns
t
h
hold time Dn to LE; see Figure 10 1.5 - - 1.5 - 1.5 - ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz;
V
I
=GNDtoV
CC
[5]
-18- - - - -pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max