Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Shift register Shift register Push pull DHVQFN 14 (2.5x3)

1. General description

The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is

pin compatible with Low-power Schottky TTL (LSTTL). It is speciﬁed in compliance with

JEDEC standard No. 7A.

The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA

or DSB); either input can be used as an active HIGH enable for data entry through the

other input. Both inputs must be connected together or an unused input must be tied

HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP)

and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB)

that existed one set-up time prior to the rising clock edge.

A LOW-level on the master reset (MR) input overrides all other inputs and clears the

2. Features

n Balanced propagation delays

n All inputs have Schmitt-trigger actions

n Inputs accept voltages higher than V

n Input levels:

u For 74AHC164: CMOS level

u For 74AHCT164: TTL level

n ESD protection:

u HBM EIA/JESD22-A114E exceeds 2000 V

u MM EIA/JESD22-A115-A exceeds 200 V

u CDM EIA/JESD22-C101C exceeds 1000 V

n Multiple package options

n Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

74AHC164; 74AHCT164

8-bit serial-in/parallel-out shift register

Rev. 03 — 24 April 2008 Product data sheet

Summary of content (18 pages)

PAGE 1
74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register Rev. 03 — 24 April 2008 Product data sheet 1. General description The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A. The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry through the other input.
PAGE 2
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AHC164D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74AHC164PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.
PAGE 3
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register SRG8 8 C1/ 9 R 1 2 & 3 1D 4 DSA DSB 1 2 8 CP 9 MR 5 3 Q0 4 Q1 6 5 Q2 10 6 Q3 10 Q4 11 Q5 12 Q6 13 Q7 11 12 13 001aac424 001aac423 Fig 2. Logic symbol Fig 3. IEC logic symbol DSA D Q D CP FF1 RD DSB Q D CP FF2 RD Q D CP FF3 RD Q D CP FF4 RD Q D CP FF5 RD Q D CP FF6 RD Q D CP FF7 RD Q CP FF8 RD CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac616 Fig 4.
PAGE 4
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 5. Pinning information 14 VCC DSB 2 13 Q7 Q0 3 Q1 4 164 terminal 1 index area 14 VCC 1 1 DSA DSA 5.1 Pinning DSB 2 13 Q7 12 Q6 Q0 3 12 Q6 11 Q5 Q1 4 164 11 Q5 Q2 5 GND(1) 10 Q4 Q3 6 5 Q3 6 9 MR 7 8 GND 7 8 CP GND CP 10 Q4 Q2 9 MR 001aac828 Transparent top view 001aac422 (1) The die substrate is attached to this pad using conductive die attach material.
PAGE 5
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 6. Functional description Table 3.
PAGE 6
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 8. Recommended operating conditions Table 5. Operating conditions Symbol Parameter Conditions Min Typ Max Unit 74AHC164 VCC supply voltage 2.0 5.0 5.5 V VI input voltage 0 - 5.5 V VO output voltage 0 - VCC V Tamb ambient temperature −40 +25 +125 °C ∆t/∆V input transition rise and fall rate VCC = 3.0 V to 3.6 V - - 100 ns/V VCC = 4.5 V to 5.
PAGE 7
4AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions VI = 5.5 V or GND; VCC = 0 V to 5.5 V −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - - 0.1 - 1.0 - 2.0 µA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 4.
PAGE 8
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max CL = 15 pF - 6.5 12.8 1.0 15.0 1.0 16.0 ns CL = 50 pF - 9.3 16.3 1.0 18.5 1.0 20.5 ns - 4.5 9.0 1.0 10.5 1.0 11.5 ns - 6.4 11.0 1.0 12.5 1.
PAGE 9
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10. Symbol Parameter trec CPD recovery time 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max VCC = 3.0 V to 3.6 V 2.5 - - 2.5 - 2.5 - ns VCC = 4.5 V to 5.5 V 2.5 - - 2.5 - 2.5 - ns - 48 - - - - - pF - 3.4 9.0 1.0 10.5 1.
PAGE 10
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 11. Waveforms 1/fmax VI CP input VM GND tW t PHL t PLH VOH VM Qn output 001aac426 VOL Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7.
PAGE 11
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register VI VM CP input GND t su t su th th VI VM DSA, DSB input GND VOH VM Qn output VOL 001aaf612 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Data set-up and hold times Table 8.
PAGE 12
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register VI negative pulse tW 90 % VM VM 10 % GND tr tf tr VI positive pulse GND tf 90 % VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance Fig 10. Load circuitry for measuring switching times Table 9.
PAGE 13
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.
PAGE 14
74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.
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74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.
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74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11.
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74AHC164; 74AHCT164 NXP Semiconductors 8-bit serial-in/parallel-out shift register 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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NXP Semiconductors 74AHC164; 74AHCT164 8-bit serial-in/parallel-out shift register 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . .