Datasheet

1. General description
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible
with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard
No. 7-A.
The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual
data inputs (D), clock inputs (CP), set inputs (S
D) and reset inputs (RD). It also has
complementary outputs (Q and Q
).
The set and reset are asynchronous active LOW inputs that operate independent of the
clock input. Information on the data input is transferred to the Q output on the LOW to
HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to
the LOW to HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock
rise and fall times.
2. Features and benefits
 Balanced propagation delays
 All inputs have Schmitt-trigger actions
 Inputs accept voltages higher than V
CC
 Input levels:
 For 74AHC74: CMOS level
 For 74AHCT74: TTL level
 ESD protection:
 HBM EIA/JESD22-A114E exceeds 2000 V
 MM EIA/JESD22-A115-A exceeds 200 V
 CDM EIA/JESD22-C101C exceeds 1000 V
 Multiple package options
 Specified from 40 C to +85 C and from 40 C to +125 C
74AHC74; 74AHCT74
Dual D-type flip-flop with set and reset; positive-edge trigger
Rev. 6 — 20 October 2014 Product data sheet