Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74AHCT DHVQFN 14 (2.5x3)

1. General description

The 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible

with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC

standard no. 7A.

The 74AHC86; 74AHCT86 provides a 2-input exclusive-OR function.

2. Features

■ Balanced propagation delays

■ All inputs have a Schmitt-trigger action

■ Inputs accepts voltages higher than V

■ For 74AHC86 only: operates with CMOS input levels

■ For 74AHCT86 only: operates with TTL input levels

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

◆ CDM JESD22-C101C exceeds 1000 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

74AHC86; 74AHCT86

Quad 2-input EXCLUSIVE-OR gate

Rev. 02 — 15 November 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74AHC86D −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm

SOT108-1

74AHCT86D

74AHC86PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74AHCT86PW

74AHC86BQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced

very thin quad ﬂat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

SOT762-1

74AHCT86BQ

Summary of content (14 pages)

PAGE 1
74AHC86; 74AHCT86 Quad 2-input EXCLUSIVE-OR gate Rev. 02 — 15 November 2007 Product data sheet 1. General description The 74AHC86; 74AHCT86 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC86; 74AHCT86 provides a 2-input exclusive-OR function. 2.
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74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 4. Functional diagram 1 2 1A 1B 1Y 3 4 5 2A 2B 2Y 6 9 10 3A 3B 3Y 8 12 13 4A 4B 4Y 11 mna787 Fig 1. Logic symbol 1 =1 3 =1 6 =1 8 =1 11 2 4 5 9 10 A 12 Y 13 B Fig 2. Logic diagram (one gate) mna788 mna786 Fig 3. IEC logic symbol 74AHC_AHCT86_2 Product data sheet © NXP B.V. 2007. All rights reserved. Rev.
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74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 5. Pinning information 1 1A terminal 1 index area 1Y 3 12 4A 2A 4 74AHC86 74AHCT86 2 13 4B 1Y 3 12 4A 2A 4 86 11 4Y 2B 5 GND(1) 10 3B 2Y 6 11 4Y 10 3B 2B 5 2Y 6 9 3A GND 7 8 3Y 9 8 2 1B 3Y 1B 14 VCC 13 4B 7 1 GND 1A 14 VCC 5.1 Pinning 3A 001aad105 Transparent top view 001aah083 (1) The die substrate is attached to this pad using conductive die attach material.
PAGE 4
74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage VI input voltage IIK input clamping current VI < −0.5 V [1] IOK output clamping current VO < −0.5 V or VO > VCC + 0.5 V [1] IO output current VO = −0.5 V to (VCC + 0.5 V) Min Max Unit −0.5 +7.0 V −0.5 +7.
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74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 9. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 - - 1.5 - 1.5 - V VCC = 3.0 V 2.1 - - 2.1 - 2.1 - V VCC = 5.5 V 3.85 - - 3.85 - 3.85 - V VCC = 2.0 V - - 0.5 - 0.5 - 0.5 V VCC = 3.0 V - - 0.9 - 0.9 - 0.
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74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate Table 6. Static characteristics …continued Voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 °C Conditions VI = 5.5 V or GND; VCC = 0 V to 5.5 V −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ Max Min Max Min Max - - 0.1 - 1.0 - 2.0 µA II input leakage current ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 2.
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4AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate Table 7. Dynamic characteristics …continued GND = 0 V; For test circuit see Figure 7. Symbol Parameter 25 °C Conditions −40 °C to +85 °C −40 °C to +125 °C Unit Min Typ[1] Max Min Max Min Max - 3.4 6.9 1.0 8.0 1.0 9.0 ns - 4.9 8.8 1.0 10.0 1.0 11.0 ns - 12.0 - - - - - pF For type 74AHCT86 propagation delay tpd nA, nB to nY; see Figure 6 [2] VCC = 4.5 V to 5.
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74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC PULSE GENERATOR VI VO RL S1 open DUT RT CL 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator CL = Load capacitance including jig and probe capacitance RL = Load resistor S1 = Test selection switch Fig 7.
PAGE 9
74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 12. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.
PAGE 10
74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.
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74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b 1 0.05 0.00 0.30 0.
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74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 13. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11.
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74AHC86; 74AHCT86 NXP Semiconductors Quad 2-input EXCLUSIVE-OR gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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NXP Semiconductors 74AHC86; 74AHCT86 Quad 2-input EXCLUSIVE-OR gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . .