Datasheet

74ALVC574_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 8 November 2007 8 of 17
NXP Semiconductors
74ALVC574
Octal D-type flip-flop; positive edge-trigger; 3-state
[1] Typical values are measured at T
amb
=25°C
[2] t
pd
is the same as t
PHL
and t
PLH
.
t
en
is the same as t
PZH
and t
PZL
.
t
dis
is the same as t
PHZ
and t
PLZ
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in µW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz; f
o
= output frequency in MHz
C
L
= output load capacitance in pF
V
CC
= supply voltage in Volts
N = number of inputs switching
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs
t
su
set-up time Dn to CP; see Figure 9
V
CC
= 1.65 V to 1.95 V 0.8 −0.1 - ns
V
CC
= 2.3 V to 2.7 V 0.8 0.1 - ns
V
CC
= 2.7 V 0.8 0.3 - ns
V
CC
= 3.0 V to 3.6 V 0.8 0.0 - ns
t
h
hold time Dn to CP; see Figure 9
V
CC
= 1.65 V to 1.95 V 0.8 −0.1 - ns
V
CC
= 2.3 V to 2.7 V 0.8 0.1 - ns
V
CC
= 2.7 V 0.8 0.4 - ns
V
CC
= 3.0 V to 3.6 V 0.7 −0.1 - ns
f
max
maximum frequency see Figure 7
V
CC
= 2.3 V to 2.7 V 100 200 - MHz
V
CC
= 2.7 V 100 200 - MHz
V
CC
= 3.0 V to 3.6 V 150 300 - MHz
C
PD
power dissipation
capacitance
per flip-flop; V
I
= GND to V
CC
;V
CC
= 3.3 V
[3]
outputs HIGH or LOW state - 21 - pF
outputs 3-state - 13 - pF
Table 7. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 10.
Symbol Parameter Conditions −40 °C to +85 °C Unit
Min Typ
[1]
Max