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74AUP1G0832 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 22 June 2012 9 of 19
NXP Semiconductors
74AUP1G0832
Low-power 3-input AND-OR gate
[1] All typical values are measured at nominal V
CC
.
[2] t
pd
is the same as t
PLH
and t
PHL
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in μW).
P
D
=C
PD
× V
CC
2
× f
i
× N+Σ(C
L
× V
CC
2
× f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
Σ(C
L
× V
CC
2
× f
o
) = sum of the outputs.
12. Waveforms
T
amb
= 25 °C
C
PD
power dissipation
capacitance
f
i
= 1 MHz; V
I
=GNDtoV
CC
[3]
V
CC
= 0.8 V - 2.5 - - - - pF
V
CC
= 1.1 V to 1.3 V - 2.7 - - - - pF
V
CC
= 1.4 V to 1.6 V - 2.8 - - - - pF
V
CC
= 1.65 V to 1.95 V - 2.9 - - - - pF
V
CC
= 2.3 V to 2.7 V - 3.4 - - - - pF
V
CC
= 3.0 V to 3.6 V - 4.0 - - - - pF
Table 9. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions 25 °C −40 °C to +125 °C Unit
Min Typ
[1]
Max Min Max
(85 °C)
Max
(125 °C)
Measurement points are given in Table 10.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 9. Input A, B and C to output Y propagation delay times