Datasheet

74AUP1G58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 15 August 2012 4 of 22
NXP Semiconductors
74AUP1G58
Low-power configurable multiple function gate
7.1 Logic configurations
Table 5. Function selection table
Logic function Figure
2-input NAND see Figure 5
2-input NAND with both inputs inverted see Figure 8
2-input AND with inverted input see Figure 6 and Figure 7
2-input NOR with inverted input see Figure 6 and Figure 7
2-input OR see Figure 8
2-input OR with both inputs inverted see Figure 5
2-input XOR see Figure 9
Buffer see Figure 10
Inverter see Figure 11
Fig 5. 2-input NAND gate or 2-input OR with both
inputs inverted
Fig 6. 2-input AND gate with inverted B input or
2-input NOR gate with inverted C input
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B
B6
Y
C1
52
43Y
Y
C
B
C
V
CC
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B
B6
Y
C1
52
43Y
Y
C
B
C
V
CC
Fig 7. 2-input AND gate with inverted C input or
2-input NOR gate with inverted A input
Fig 8. 2-input OR gate or 2-input NAND gate with
both inputs inverted
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A
A
6
Y
C1
52
43Y
Y
C
A
C
V
CC
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A
6C1
52
43Y
V
CC
A
Y
C
Y
A
C
Fig 9. 2-input XOR gate Fig 10. Buffer
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B6C1
52
43Y
V
CC
Y
B
C
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A
A
6
Y
1
52
43Y
V
CC