Datasheet

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9 — 6 January 2014 15 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
12. Waveforms
Measurement points are given in Table 10.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 8. The clock input (CP) to output (Q, Q) propagation delays, the data input (D) to clock input (CP) set-up and
hold times and the clock input (CP) pulse width and maximum frequency
001aae365
t
h
t
su
t
h
t
PHL
t
PLH
t
PLH
t
PHL
t
su
1/f
max
V
M
V
M
V
M
t
W
V
M
V
I
GND
V
I
GND
CP input
D input
V
OH
V
OL
V
OH
V
OL
Q output
Q output
Table 10. Measurement points
Supply voltage Output Input
V
CC
V
M
V
M
V
I
t
r
= t
f
0.8 V to 3.6 V 0.5  V
CC
0.5  V
CC
V
CC
 3.0 ns