Datasheet

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9 — 6 January 2014 16 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
Measurement points are given in Table 10.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 9. The set input (SD) and reset input (RD) to output (Q, Q) propagation delays, the set input (SD) and reset
input (RD) pulse widths and the reset input (RD) to clock input (CP) recovery time
001aae366
RD input
SD input
CP input
Q output
Q output
t
PLH
t
rec
t
rec
t
W
t
PHL
t
W
V
M
V
OH
V
OH
V
OL
V
OL
V
M
V
M
t
PLH
V
M
t
PHL
V
M
V
I
GND
V
I
GND
V
I
GND