Datasheet

74AUP1G74 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved.
Product data sheet Rev. 9 — 6 January 2014 3 of 28
NXP Semiconductors
74AUP1G74
Low-power D-type flip-flop with set and reset; positive-edge trigger
6. Pinning information
6.1 Pinning
Fig 3. Logic diagram
001aae087
SD
CP
RD
D
Q
C
C
C
C
C
C
Q
C
C
Fig 4. Pin configuration SOT765-1 Fig 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP1G74
CP V
CC
DSD
QRD
GND Q
001aae322
1
2
3
4
6
5
8
7
74AUP1G74
RD
SD
V
CC
Q
Q
D
CP
GND
001aae323
36
27
18
45
Transparent top view