Datasheet

74AUP1T58 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 5 — 15 August 2012 10 of 20
NXP Semiconductors
74AUP1T58
Low-power configurable gate with voltage-level translator
12. Waveforms
Measurement points are given in Table 10.
V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 12. Input A, B and C to output Y propagation delay times
Y output
A, B, C input
Y output
GND
V
I
V
OH
V
OH
V
OL
V
OL
V
M
V
M
V
M
V
M
V
M
V
M
t
PLH
t
PLH
t
PHL
t
PHL
001aab593
Table 10. Measurement points
Supply voltage Output Input
V
CC
V
M
V
M
V
I
t
r
= t
f
2.3 V to 3.6 V 0.5  V
CC
0.5  V
I
1.65 V to 3.6 V  3.0 ns