Datasheet

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1. General description

The 74AUP2G0604 is a single inverting buffer with open-drain output and a single

inverter. It features two input pins (nA), an output pin (2Y) and an open-drain output pin

(1Y).

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing the damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 0.8 V to 3.6 V

 High noise immunity

 Complies with JEDEC standards:

 JESD8-12 (0.8 V to 1.3 V)

 JESD8-11 (0.9 V to 1.65 V)

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-B (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F Class 3A exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V

 CDM JESD22-C101E exceeds 1000 V

 Low static power consumption; I

= 0.9 A (maximum)

 Latch-up performance exceeds 100 mA per JESD 78 Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V

 I

OFF

circuitry provides partial power-down mode operation

 Multiple package options

 Specified from 40 Cto+85C and 40 Cto+125C

74AUP2G0604

Low-power inverting buffer with open-drain and inverter

Rev. 1 — 23 November 2012 Product data sheet

Summary of content (20 pages)

PAGE 1
74AUP2G0604 Low-power inverting buffer with open-drain and inverter Rev. 1 — 23 November 2012 Product data sheet 1. General description The 74AUP2G0604 is a single inverting buffer with open-drain output and a single inverter. It features two input pins (nA), an output pin (2Y) and an open-drain output pin (1Y). Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74AUP2G0604GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363 74AUP2G0604GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads; 6 terminals; body 1  1.45  0.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 6. Pinning information 6.1 Pinning $83 * $83 * $83 * $ < *1' 9&& $ < *1' 9&& $ < < Fig 5. Pin configuration SOT886 < *1' 9&& $ < 7UDQVSDUHQW WRS YLHZ 7UDQVSDUHQW WRS YLHZ Pin configuration SOT363 DDD DDD DDD Fig 4. $ $ Fig 6. Pin configuration SOT891, SOT1115 and SOT1202 6.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current Conditions Min Max Unit 0.5 +4.6 V 50 - mA 0.5 +4.6 V 50 - mA 0.5 +4.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 10. Static characteristics Table 8. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V VCC = 0.9 V to 1.95 V Typ Max Unit 0.70  VCC - - V 0.65  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.30  VCC V VCC = 0.9 V to 1.95 V - - 0.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions CO VO = GND; VCC = 0 V output capacitance 1Y output; enabled Min Typ Max Unit - 1.7 - pF 1Y output; disabled - 1.1 - pF 2Y output - 1.
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4AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter Table 8. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min VCC = 0.8 V Typ Max Unit 0.75  VCC - - V VCC = 0.9 V to 1.95 V 0.70  VCC - - V VCC = 2.3 V to 2.7 V 1.6 - - V VCC = 3.0 V to 3.6 V 2.0 - - V VCC = 0.8 V - - 0.25  VCC V VCC = 0.9 V to 1.95 V - - 0.30  VCC V VCC = 2.3 V to 2.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 11. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min - 14.4 - - - - ns Max Max (85 C) (125 C) CL = 5 pF tpd propagation 1A to 1Y or 2A to 2Y; see Figure 7 delay VCC = 0.8 V [2] VCC = 1.1 V to 1.3 V 2.3 4.7 10.3 2.0 11.4 12.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter Table 9. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 8. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min - 0.5 - - - - pF - 0.6 - - - - pF Max Max (85 C) (125 C) CL = 5 pF, 10 pF, 15 pF and 30 pF power 1A to 1Y; fi=1 MHz; VI = GND to VCC dissipation VCC = 0.8 V capacitance VCC = 1.1 V to 1.
PAGE 10
74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 12. Waveforms 9, 9, $ LQSXW 90 $ LQSXW 90 90 *1' *1' W3+/ W3=/ W3/= 9&& W3/+ 92+ < RXWSXW < RXWSXW 90 9; 92/ 90 90 92/ Measurement points are given in Table 10. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. Fig 7. Table 10.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter VCC VEXT 5 kΩ G VI VO DUT CL RT RL 001aac521 Test data is given in Table 11. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig 8. Table 11.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 13. Package outline Plastic surface-mounted package; 6 leads SOT363 D E B y X A HE 6 5 v M A 4 Q pin 1 index A A1 1 2 e1 3 bp c Lp w M B e detail X 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A A1 max bp c D E e e1 HE Lp Q v w y mm 1.1 0.8 0.1 0.30 0.20 0.25 0.10 2.2 1.8 1.35 1.15 1.3 0.65 2.2 2.0 0.45 0.15 0.25 0.15 0.2 0.2 0.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter SOT886 XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1.45 x 0.5 mm b 1 2 3 4x (2) L L1 e 6 5 e1 4 e1 6x A (2) A1 D E terminal 1 index area 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit max nom min mm A(1) 0.5 A1 b D E 0.04 0.25 1.50 1.05 0.20 1.45 1.00 0.17 1.40 0.95 e e1 0.6 0.5 L L1 0.35 0.40 0.30 0.35 0.27 0.32 Notes 1.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1 x 0.5 mm 1 SOT891 b 3 2 4× (1) L L1 e 6 5 4 e1 e1 6× A (1) A1 D E terminal 1 index area 0 1 2 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max A1 max b D E e e1 L L1 mm 0.5 0.04 0.20 0.12 1.05 0.95 1.05 0.95 0.55 0.35 0.35 0.27 0.40 0.32 Note 1.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1.0 x 0.35 mm 1 SOT1115 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 Dimensions Unit A(1) A1 b D E e e1 max 0.35 0.04 0.20 0.95 1.05 nom 0.15 0.90 1.00 0.55 min 0.12 0.85 0.95 mm 1 mm scale L L1 0.35 0.40 0.30 0.35 0.27 0.32 0.3 Note 1. Including plating thickness. 2.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1.0 x 0.35 mm 1 SOT1202 b 3 2 (4×)(2) L L1 e 6 5 4 e1 e1 (6×)(2) A1 A D E terminal 1 index area 0 0.5 scale Dimensions Unit 1 mm A(1) A1 b D E e e1 L L1 max 0.35 0.04 0.20 1.05 1.05 0.35 0.40 nom 0.15 1.00 1.00 0.55 0.35 0.30 0.35 min 0.12 0.95 0.95 0.27 0.32 mm Note 1. Including plating thickness. 2.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74AUP2G0604 v.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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74AUP2G0604 NXP Semiconductors Low-power inverting buffer with open-drain and inverter 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . .