Datasheet

74AUP2G0604 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 23 November 2012 2 of 20
NXP Semiconductors
74AUP2G0604
Low-power inverting buffer with open-drain and inverter
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP2G0604GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
74AUP2G0604GM 40 C to +125 C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1  1.45  0.5 mm
SOT886
74AUP2G0604GF 40 C to +125 C XSON6 plastic extremely thin small outline package;
no leads; 6 terminals; body 1  1  0.5 mm
SOT891
74AUP2G0604GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9  1.0  0.35 mm
SOT1115
74AUP2G0604GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0  1.0  0.35 mm
SOT1202
Table 2. Marking
Type number Marking code
[1]
74AUP2G0604GW a6
74AUP2G0604GM a6
74AUP2G0604GF a6
74AUP2G0604GN a6
74AUP2G0604GS a6
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram
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