Datasheet

74AUP2G07 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 29 November 2012 2 of 18
NXP Semiconductors
74AUP2G07
Low-power dual buffer with open-drain output
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP2G07GW 40 C to +125 C SC-88 plastic surface-mounted package; 6 leads SOT363
74AUP2G07GM 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1  1.45  0.5 mm
SOT886
74AUP2G07GF 40 C to +125 C XSON6 plastic extremely thin small outline package; no leads;
6 terminals; body 1  1  0.5 mm
SOT891
74AUP2G07GN 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 0.9  1.0  0.35 mm
SOT1115
74AUP2G07GS 40 C to +125 C XSON6 extremely thin small outline package; no leads;
6 terminals; body 1.0  1.0  0.35 mm
SOT1202
Table 2. Marking
Type number Marking code
[1]
74AUP2G07GW p7
74AUP2G07GM p7
74AUP2G07GF p7
74AUP2G07GN p7
74AUP2G07GS p7
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
mnb092
1A 1Y
1
6
2A 2Y
3
4
6
1
1A
1Y
mnb093
4
3
2A
2Y
mna625
A
Y
GND