Datasheet

74AUP2G07 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 7 — 29 November 2012 9 of 18
NXP Semiconductors
74AUP2G07
Low-power dual buffer with open-drain output
[1] For measuring enable and disable times R
L
= 5 k, for measuring propagation delays, set-up and hold times and pulse width
R
L
=1M.
Test data is given in Table 10
.
Definitions for test circuit:
R
L
= Load resistance.
C
L
= Load capacitance including jig and probe capacitance.
R
T
= Termination resistance should be equal to the output impedance Z
o
of the pulse generator.
V
EXT
= External voltage for measuring switching times.
Fig 8. Test circuit for measuring switching times
001aac521
DUT
R
T
V
I
V
O
V
EXT
V
CC
R
L
5 kΩ
C
L
G
Table 10. Test data
Supply voltage Input Load V
EXT
V
CC
V
I
t
r
, t
f
C
L
R
L
[1]
t
PLH
, t
PHL
t
PZH
, t
PHZ
t
PZL
, t
PLZ
0.8 V to 3.6 V V
CC
 3 ns 5 pF, 10 pF, 15 pF and 30 pF 5 k or 1 M open GND 2  V
CC