Datasheet
74AUP2G126 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 9 — 11 February 2013 2 of 24
NXP Semiconductors
74AUP2G126
Low-power dual buffer/line driver; 3-state
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP2G126DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74AUP2G126GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 1.95 0.5 mm
SOT833-1
74AUP2G126GF 40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 1 0.5 mm
SOT1089
74AUP2G126GD 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 3 2 0.5 mm
SOT996-2
74AUP2G126GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 1.6 0.5 mm
SOT902-2
74AUP2G126GN 40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2 1.0 0.35 mm
SOT1116
74AUP2G126GS 40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking codes
Type number Marking code
[1]
74AUP2G126DC p26
74AUP2G126GT p26
74AUP2G126GF pN
74AUP2G126GD p26
74AUP2G126GM p26
74AUP2G126GN pN
74AUP2G126GS pN
Fig 1. Logic symbol Fig 2. Logic diagram (one gate)
001aah787
2A
1A
2OE
1OE
1Y
2Y
mna234
nOE
nA
nY