Datasheet

74AUP2G132 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 8 February 2013 2 of 23
NXP Semiconductors
74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
4. Ordering information
5. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
6. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AUP2G132DC 40 C to +125 C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74AUP2G132GT 40 C to +125 C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1  1.95  0.5 mm
SOT833-1
74AUP2G132GF 40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35  1  0.5 mm
SOT1089
74AUP2G132GD 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 3  2  0.5 mm
SOT996-2
74AUP2G132GM 40 C to +125 C XQFN8 plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6  1.6  0.5 mm
SOT902-2
74AUP2G132GN 40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2  1.0  0.35 mm
SOT1116
74AUP2G132GS 40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35  1.0  0.35 mm
SOT1203
Table 2. Marking codes
Type number Marking code
[1]
74AUP2G132DC aE2
74AUP2G132GT aE2
74AUP2G132GF aE
74AUP2G132GD aE2
74AUP2G132GM aE2
74AUP2G132GN aE
74AUP2G132GS aE
Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one gate)
001aah880
1A
1B
1Y
2A
2B
2Y
001aah881
&
&
001aac532
Y
B
A