Datasheet

74AUP2G132 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 7 — 8 February 2013 3 of 23
NXP Semiconductors
74AUP2G132
Low-power dual 2-input NAND Schmitt trigger
7. Pinning information
7.1 Pinning
7.2 Pin description
Fig 4. Pin configuration SOT765-1 Fig 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP2G132
1A V
CC
1B 1Y
2Y 2B
GND 2A
001aaf164
1
2
3
4
6
5
8
7
74AUP2G132
2B
1Y
V
CC
2A
2Y
1B
1A
GND
001aaf165
36
27
18
45
Transparent top view
Fig 6. Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-2
001aaj264
74AUP2G132
Transparent top view
8
7
6
5
1
2
3
4
1A
1B
2Y
GND
V
CC
1Y
2B
2A
001aaf166
1B2B
1A
V
CC
2Y
1Y
GND
2A
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74AUP2G132
Table 3. Pin description
Symbol Pin Description
SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203
SOT902-2
1A, 2A 1, 5 7, 3 data input
1B, 2B 2, 6 6, 2 data input
GND 4 4 ground (0 V)
1Y, 2Y 7, 3 1, 5 data output
V
CC
8 8 supply voltage