Datasheet

74AUP2G86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 24 January 2013 11 of 21
NXP Semiconductors
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
13. Package outline
Fig 10. Package outline SOT765-1 (VSSOP8)
UNIT
A
1
A
max.
A
2
A
3
b
p
LH
E
L
p
wyv
ceD
(1)
E
(2)
Z
(1)
θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC JEITA
mm
0.15
0.00
0.85
0.60
0.27
0.17
0.23
0.08
2.1
1.9
2.4
2.2
0.5
3.2
3.0
0.4
0.1
8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187
02-06-07
w M
b
p
D
Z
e
0.12
14
8
5
θ
A
2
A
1
Q
L
p
(A
3
)
detail X
A
L
H
E
E
c
v M
A
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm
SOT765-1
1
pin 1 index