Datasheet

74AUP2G86 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 8 — 24 January 2013 3 of 21
NXP Semiconductors
74AUP2G86
Low-power dual 2-input EXCLUSIVE-OR gate
6. Pinning information
6.1 Pinning
Fig 3. Logic diagram (one gate)
mna040
Y
B
A
Fig 4. Pin configuration SOT765-1 Fig 5. Pin configuration SOT833-1, SOT1089,
SOT1116 and SOT1203
74AUP2G86
1A V
CC
1B 1Y
2Y 2B
GND 2A
001aaf173
1
2
3
4
6
5
8
7
74AUP2G86
2B
1Y
V
CC
2A
2Y
1B
1A
GND
001aaf174
36
27
18
45
Transparent top view
Fig 6. Pin configuration SOT996-2 Fig 7. Pin configuration SOT902-2
001aaj918
74AUP2G86
Transparent top view
8
7
6
5
1
2
3
4
1A
1B
2Y
GND
V
CC
1Y
2B
2A
001aaf175
1B2B
1A
V
CC
2Y
1Y
GND
2A
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74AUP2G86