Datasheet
Table Of Contents
- 1. General description
- 2. Features and benefits
- 3. Ordering information
- 4. Marking
- 5. Functional diagram
- 6. Pinning information
- 7. Functional description
- 8. Limiting values
- 9. Recommended operating conditions
- 10. Static characteristics
- 11. Dynamic characteristics
- 12. Waveforms
- 13. Typical propagation delay characteristics
- 14. Package outline
- 15. Abbreviations
- 16. Revision history
- 17. Legal information
- 18. Contact information
- 19. Contents
74AVC4T245 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 4 — 7 December 2011 2 of 27
NXP Semiconductors
74AVC4T245
4-bit dual supply translating transceiver; 3-state
100 Mbit/s ( 1.1 V to 1.2 V translation)
Suspend mode
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 Cto+85C and 40 Cto+125C
3. Ordering information
4. Marking
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AVC4T245D 40 Cto+125C SO16 plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
74AVC4T245PW 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74AVC4T245BQ 40 C to +125 C DHVQFN16 plastic dual in-line compatible thermal enhanced very
thin quad flat package; no leads; 16 terminals;
body 2.5 3.5 0.85 mm
SOT763-1
74AVC4T245GU 40 C to +125 C XQFN16 plastic, extremely thin quad flat package; no leads;
16 terminals; body 1.80 2.60 0.50 mm
SOT1161-1
Table 2. Marking codes
Type number Marking code
74AVC4T245D 74AVC4T245D
74AVC4T245PW VC4T245
74AVC4T245BQ C4T245
74AVC4T245GU BT5