Datasheet

74AVCH2T45 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 6 — 2 April 2013 2 of 27
NXP Semiconductors
74AVCH2T45
Dual-bit, dual-supply voltage level translator/transceiver; 3-state
280 Mbps (translate to 1.5 V)
240 Mbps (translate to 1.2 V)
Suspend mode
Bus hold on data inputs
Latch-up performance exceeds 100 mA per JESD 78 Class II
Inputs accept voltages up to 3.6 V
Low noise overshoot and undershoot < 10 % of V
CC
I
OFF
circuitry provides partial Power-down mode operation
Multiple package options
Specified from 40 Cto+85C and 40 Cto+125C
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74AVCH2T45DC 40 Cto+125C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm
SOT765-1
74AVCH2T45GT 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 1.95 0.5 mm
SOT833-1
74AVCH2T45GF 40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 1 0.5 mm
SOT1089
74AVCH2T45GD 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 3 2 0.5 mm
SOT996-2
74AVCH2T45GN 40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2 1.0 0.35 mm
SOT1116
74AVCH2T45GS 40 C to +125 C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 1.0 0.35 mm
SOT1203
Table 2. Marking
Type number Marking code
[1]
74AVCH2T45DC K45
74AVCH2T45GT K45
74AVCH2T45GF K5
74AVCH2T45GD K45
74AVCH2T45GN K5
74AVCH2T45GS K5