Datasheet

74HC_HCT107 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 16 of 19
NXP Semiconductors
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
LSTTL Low-power Schottky Transistor-Transistor Logic
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
CDM Charge-Device Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC_HCT107 v.4 20150126 Product data sheet - 74HC_HCT107 v.3
Modifications:
• Table 7: Power dissipation capacitance condition for 74HCT107 is corrected.
74HC_HCT107 v.3 20131118 Product data sheet - 74HC_HCT107_CNV v.2
Modifications:
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
74HC_HCT107_CNV v.2 19901201 Product specification - -