Datasheet

74HC_HCT107 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 26 January 2015 7 of 19
NXP Semiconductors
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
10. Dynamic characteristics
Table 7. Dynamic characteristics
GND (ground = 0 V); C
L
= 50 pF unless otherwise specified; for test circuit, see Figure 7
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ Max Min Max Min Max
74HC107
t
pd
propagation
delay
nCP to nQ; see Figure 5
[1]
V
CC
= 2.0 V - 52 160 - 200 - 240 ns
V
CC
= 4.5 V - 19 32 - 40 - 48 ns
V
CC
=5.0V; C
L
=15pF - 16 - - - - - ns
V
CC
= 6.0 V - 15 27 - 34 - 41 ns
nCP
to nQ; see Figure 5
V
CC
= 2.0 V - 52 160 - 200 - 240 ns
V
CC
= 4.5 V - 19 32 - 40 - 48 ns
V
CC
=5.0V; C
L
=15pF - 16 - - - - - ns
V
CC
= 6.0 V - 15 27 - 34 - 41 ns
nR
to nQ, nQ; see Figure 6
V
CC
= 2.0 V - 52 155 - 195 - 235 ns
V
CC
= 4.5 V - 19 31 - 39 - 47 ns
V
CC
=5.0V; C
L
=15pF - 16 - - - - - ns
V
CC
= 6.0 V - 15 26 - 33 - 40 ns
t
t
transition time nQ, nQ; see Figure 5
[2]
V
CC
= 2.0 V - 19 75 - 95 - 110 ns
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
V
CC
= 6.0 V - 6 13 - 16 - 19 ns
t
W
pulse width nCP input, HIGH or LOW;
see Figure 5
V
CC
= 2.0 V 80 22 - 100 - 120 - ns
V
CC
= 4.5 V 16 8 - 20 - 24 - ns
V
CC
= 6.0 V 14 6 - 17 - 20 - ns
nR
input, HIGH or LOW;
see Figure 6
V
CC
= 2.0 V 80 22 - 100 - 120 - ns
V
CC
= 4.5 V 16 8 - 20 - 24 - ns
V
CC
= 6.0 V 14 6 - 17 - 20 - ns
t
rec
recovery time nR to nCP; see Figure 6
V
CC
= 2.0 V 60 19 - 75 - 90 - ns
V
CC
= 4.5 V 12 7 - 15 - 18 - ns
V
CC
= 6.0 V 20 6 - 13 - 15 - ns
t
su
set-up time nJ, nK to nCP; see Figure 5
V
CC
= 2.0 V 100 22 - 125 - 150 - ns
V
CC
= 4.5 V 20 8 - 25 - 30 - ns
V
CC
= 6.0 V 17 6 - 21 - 26 - ns