Datasheet
Table Of Contents
- 1. General description
- 2. Features
- 3. Ordering information
- 4. Functional diagram
- 5. Pinning information
- 6. Functional description
- 7. Limiting values
- 8. Recommended operating conditions
- 9. Static characteristics
- 10. Dynamic characteristics
- 11. Waveforms
- 12. Package outline
- 13. Abbreviations
- 14. Revision history
- 15. Legal information
- 16. Contact information
- 17. Contents

1. General description
The 74HC11; 74HCT11 are high-speed Si-gate CMOS devices that comply with JEDEC
standard no. 7A. They are pin compatible with Low-power Schottky TTL (LSTTL).
The 74HC11; 74HCT11 provides a triple 3-input AND function.
2. Features
Input levels:
For 74HC11: CMOS level
For 74HCT11: TTL level
ESD protection:
HBM JESD22-A114F exceeds 2 000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
3. Ordering information
74HC11; 74HCT11
Triple 3-input AND gate
Rev. 04 — 25 March 2010 Product data sheet
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74HC11N −40 °C to +125 °C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HCT11N
74HC11D −40 °C to +125 °C SO14 plastic small outline package; 14 leads; body width
3.9
mm
SOT108-1
74HCT11D
74HC11DB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads; body
width 5.3
mm
SOT337-1
74HCT11DB
74HC11PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4
mm
SOT402-1
74HCT11PW