Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Demultiplexer, decoder Decoder/demultiplexer Single supply SO 16

1. General description

The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power

Schottky TTL (LSTTL). The 74HC137 is speciﬁed in compliance with JEDEC

standard no. 7A.

The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address

inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit

storage latch. When the latch is enabled (LE = LOW), the 74HC137 acts as a 3-to-8 active

LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the last data present

at the inputs before this transition, is stored in the latches. Further address changes are

ignored as long as LE remains HIGH.

The output enable input (E1 and E2) controls the state of the outputs independent of the

address inputs or latch operation. All outputs are HIGH unless E1 is LOW and E2 is HIGH.

The 74HC137 is ideally suited for implementing non-overlapping decoders in 3-state

systems and strobed (stored address) applications in bus oriented systems.

2. Features

■ Combines 3-to-8 decoder with 3-bit latch

■ Multiple input enable for easy expansion or independent controls

■ Active LOW mutually exclusive outputs

■ Low-power dissipation

■ Complies with JEDEC standard no. 7A

■ ESD protection:

◆ HBM EIA/JESD22-A114-B exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V.

■ Multiple package options

■ Speciﬁed from −40 °Cto+80°C and from −40 °C to +125 °C.

74HC137

3-to-8 line decoder, demultiplexer with address latches;

inverting

Rev. 03 — 11 November 2004 Product data sheet

Summary of content (19 pages)

PAGE 1
74HC137 3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 — 11 November 2004 Product data sheet 1. General description The 74HC137 is a high-speed Si-gate CMOS device and is pin compatible with low power Schottky TTL (LSTTL). The 74HC137 is specified in compliance with JEDEC standard no. 7A. The 74HC137 is a 3-to-8 line decoder, demultiplexer with latches at the three address inputs (An). The 74HC137 essentially combines the 3-to-8 decoder function with a 3-bit storage latch.
PAGE 2
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol Parameter Conditions tPHL, tPLH propagation delay CL = 15 pF; VCC = 5 V Typ Max Unit An to Yn - 18 - ns LE to Yn - 17 - ns E1 to Yn - 15 - ns E2 to Yn - 15 - ns CI input capacitance CPD power dissipation capacitance [1] Min VI = GND to VCC [1] - 3.
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74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 5. Functional diagram 4 LE Y0 15 Y1 14 Y2 13 1 A0 Y3 12 2 A1 INPUT LATCHES 3 A2 3 TO 8 DECODER Y4 11 Y5 10 Y6 9 Y7 7 5 E1 6 E2 001aab881 Fig 1.
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74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting A0 A0 LATCH LE Y0 A0 LE Y1 A1 A1 LATCH LE A1 LE Y2 A2 A2 LATCH LE Y3 A2 LE Y4 LE Y5 Y6 Y7 E1 001aab882 E2 Fig 4. Logic diagram 6. Pinning information 6.1 Pinning A0 1 16 VCC A1 2 15 Y0 A2 3 14 Y1 LE 4 13 Y2 137 E1 5 12 Y3 E2 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 001aab878 Fig 5. Pin configuration 9397 750 13804 Product data sheet © Koninklijke Philips Electronics N.
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74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 6.
PAGE 6
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 8. Limiting values Table 5: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit VCC supply voltage IIK input diode current VI < −0.5 V or VI > VCC + 0.5 V −0.5 +7 V - ±20 mA IOK output diode current VO < −0.5 V or VO > VCC + 0.
PAGE 7
4HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 10. Static characteristics Table 7: Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit Tamb = 25 °C VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V 1.5 1.2 - V VCC = 4.5 V 3.15 2.4 - V VCC = 6.0 V 4.2 3.
PAGE 8
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting Table 7: Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Typ Max Unit VOL LOW-level output voltage VI = VIH or VIL IO = 20 µA; VCC = 2.0 V - - 0.1 V IO = 20 µA; VCC = 4.5 V - - 0.1 V IO = 20 µA; VCC = 6.0 V - - 0.1 V IO = 4 mA; VCC = 4.5 V - - 0.33 V IO = 5.2 mA; VCC = 6.
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74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 11. Dynamic characteristics Table 8: Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF. Symbol Parameter Conditions Min Typ Max Unit VCC = 2.0 V - 58 180 ns VCC = 4.5 V - 21 36 ns VCC = 6.0 V - 17 31 ns VCC = 5.0 V; CL = 15 pF - 18 - ns VCC = 2.0 V - 55 190 ns VCC = 4.
PAGE 10
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
PAGE 11
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting Table 8: Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF.
PAGE 12
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 12. Waveforms An, E2 input VM tPHL Yn output tPLH VM tTHL tTLH 001aab883 VM = 0.5 × VI. Fig 6. Waveforms showing the address input (An) and enable input (E2) to output (Yn) propagation delays and the output transition times E1, LE input VM tPHL Yn output tPLH VM tTHL tTLH 001aab884 VM = 0.5 × VI. Fig 7.
PAGE 13
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting VCC PULSE GENERATOR VI VO D.U.T. CL RT mna101 Test data is given in Table 9. Definitions for test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. Fig 9. Load circuitry for switching times Table 9: Test data Supply Input Load VCC VI tr, tf CL 2.0 V VCC 6 ns 50 pF 4.
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74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 14. Package outline DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b b2 MH 9 16 pin 1 index E 1 8 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 b2 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.30 0.53 0.
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74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.
PAGE 16
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.
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74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 15. Revision history Table 10: Revision history Document ID Release date 74HC137_3 20041111 Product data sheet Modifications: Data sheet status Change notice Doc. number Supersedes - 9397 750 13804 74HC_HCT137_CNV_2 • The format of this data sheet has been redesigned to comply with the current presentation and information standard of Philips Semiconductors. • • Removed type number 74HCT137.
PAGE 18
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 16. Data sheet status Level Data sheet status [1] Product status [2] [3] Definition I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification.
PAGE 19
74HC137 Philips Semiconductors 3-to-8 line decoder, demultiplexer with address latches; inverting 20. Contents 1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 12 13 14 15 16 17 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . .