Datasheet

December 1990 12
Philips Semiconductors Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines” .
Fig.11 Waveforms showing the set-up and hold times for the input (D
n
) and parallel enable input PE.
The shaded areas indicate when the input is permitted to change
for predictable output performance.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.12 Waveforms showing the CEP and CET set-up and hold times.
The shaded areas indicate when the input is
permitted to change for predictable output
performance.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.