Datasheet
1. General description
The 74HC163; 74HCT163 is a synchronous presettable binary counter with an internal
look-head carry. Synchronous operation is provided by having all flip-flops clocked
simultaneously on the positive-going edge of the clock (CP). The outputs (Q0 to Q3) of the
counters may be preset to a HIGH or LOW. A LOW at the parallel enable input (PE
)
disables the counting action. It causes the data at the data inputs (D0 to D3) to be loaded
into the counter on the positive-going edge of the clock. Preset takes place regardless of
the levels at count enable inputs (CEP and CET). A LOW at the master reset input (MR
)
sets Q0 to Q3 LOW after the next positive-going transition on the clock input (CP). This
action occurs regardless of the levels at input pins PE
, CET and CEP. This synchronous
reset feature enables the designer to modify the maximum count with only one external
NAND gate. The look-ahead carry simplifies serial cascading of the counters. Both CEP
and CET must be HIGH to count. The CET input is fed forward to enable the terminal
count output (TC). The TC output thus enabled will produce a HIGH output pulse of a
duration approximately equal to a HIGH output of Q0. This pulse can be used to enable
the next cascaded stage. Inputs include clamp diodes. This enables the use of current
limiting resistors to interface inputs to voltages in excess of V
CC
.
The CP to TC propagation delay and CEP to CP set-up time determine the maximum
clock frequency for the cascaded counters according to the following formula:
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
For 74HC163: CMOS level
For 74HCT163: TTL level
Synchronous counting and loading
2 count enable inputs for n-bit cascading
Synchronous reset
Positive-edge triggered clock
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
74HC163; 74HCT163
Presettable synchronous 4-bit binary counter; synchronous
reset
Rev. 3 — 2 June 2014 Product data sheet
f
max
1
t
Pmax
CPtoTCt
SU
CEPtoCP+
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