74HC164; 74HCT164 8-bit serial-in, parallel-out shift register Rev. 7 — 13 June 2013 Product data sheet 1. General description The 74HC164; 74HCT164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register 3. Ordering information Table 1. Ordering information Type number 74HC164N Package Temperature range Name Description Version 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register DSA D Q D CP FF1 RD DSB Q D CP FF2 RD Q D CP FF3 RD Q D CP FF4 RD Q D CP FF5 RD Q D CP FF6 RD Q D CP FF7 RD Q CP FF8 RD CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac616 Fig 4. Functional diagram 5. Pinning information 5.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register 5.2 Pin description Table 2. Pin description Symbol Pin Description DSA 1 data input DSB 2 data input Q0 to Q7 3, 4, 5, 6, 10, 11, 12, 13 output GND 7 ground (0 V) CP 8 clock input (LOW-to-HIGH, edge-triggered) MR 9 master reset input (active LOW) VCC 14 positive supply voltage 6. Functional description Table 3.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register Table 4. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Ptot [1] [2] Parameter Conditions Min Max Unit DIP14 package - 750 mW SO14, (T)SSOP14 and DHVQFN14 packages - 500 mW [2] total power dissipation The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH VOL HIGH-level output voltage LOW-level output voltage 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VI = VIH or VIL IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.
4HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified Symbol Parameter 25 C Conditions Min 40 C to +85 C Typ Max 40 C to +125 C Unit Min Max Min Max 74HC164 tpd tPHL propagation delay HIGH to LOW propagation delay [1] CP to Qn; see Figure 7 VCC = 2.0 V - 41 170 - 215 - 255 ns VCC = 4.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified Symbol Parameter 25 C Conditions Min fmax maximum frequency Min Max Min Max VCC = 2.0 V 6 23 - 5 - 4 - MHz VCC = 4.5 V 30 71 - 24 - 20 - MHz - 78 - - - - - MHz 35 85 - 28 - 24 - MHz - 40 - - - - - pF VCC = 4.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit see Figure 10; unless otherwise specified Symbol Parameter 25 C Conditions Min CPD [1] power dissipation capacitance [3] per package; VI = GND to VCC 1.5 V - 40 C to +85 C Typ Max 40 - 40 C to +125 C Unit Min Max Min Max - - - - pF tpd is the same as tPHL and tPLH.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register VI VM MR input GND tW frec VI CP input VM GND tPHL VOH VM Qn output VOL 001aac427 (1) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 10. Test circuit for measuring switching times Table 9.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register 11. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. A1 b 1 0.05 0.00 0.30 0.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11.
74HC164; 74HCT164 NXP Semiconductors 8-bit serial-in, parallel-out shift register 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
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NXP Semiconductors 74HC164; 74HCT164 8-bit serial-in, parallel-out shift register 16. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . .