INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT173 Quad D-type flip-flop; positive-edge trigger; 3-state Product specification File under Integrated Circuits, IC06 December 1990
Philips Semiconductors Product specification Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173 synchronously with the LOW-to-HIGH clock (CP) transition. When one or both En inputs are HIGH one set-up time prior to the LOW-to-HIGH clock transition, the register will retain the previous data. Data inputs and clock enable inputs are fully edge-triggered and must be stable only one set-up time prior to the LOW-to-HIGH clock transition.
Philips Semiconductors Product specification Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173 PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1, 2 OE1, OE2 output enable input (active LOW) 3, 4, 5, 6 Q0 to Q3 3-state flip-flop outputs 7 CP clock input (LOW-to-HIGH, edge-triggered) 8 GND ground (0 V) 9, 10 E1, E2 data enable inputs (active LOW) 14, 13, 12, 11 D0 to D3 data inputs 15 MR asynchronous master reset (active HIGH) 16 VCC positive supply voltage Fig.
Philips Semiconductors Product specification Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173 Fig.4 Functional diagram.
Philips Semiconductors Product specification Quad D-type flip-flop; positive-edge trigger; 3-state Fig.5 Logic diagram.
Philips Semiconductors Product specification Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173 DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. UNIT V WAVEFORMS CC (V) max.
Philips Semiconductors Product specification Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173 Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER +25 −40 to +85 −40 to +125 min. typ. max. min. max. min. WAVEFORMS UNIT V CC (V) max. th hold time En to CP 0 0 0 −17 −6 −5 0 0 0 0 0 0 ns 2.0 4.5 6.0 Fig.9 th hold time Dn to CP 1 1 1 −11 −4 −3 1 1 1 1 1 1 ns 2.0 4.5 6.0 Fig.9 fmax maximum clock pulse frequency 6.0 30 35 26 80 95 4.8 24 28 4.0 20 24 MHz 2.0 4.
Philips Semiconductors Product specification Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”. Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
Philips Semiconductors Product specification Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER +25 −40 to +85 −40 to +125 UNIT V CC (V) WAVEFORMS min. typ. max. min. max. min. max. tPHL/ tPLH propagation delay CP to Qn 20 40 50 60 ns 4.5 Fig.6 tPHL propagation delay MR to Qn 20 37 46 56 ns 4.5 Fig.
Philips Semiconductors Product specification Quad D-type flip-flop; positive-edge trigger; 3-state 74HC/HCT173 AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Fig.7 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency.