Datasheet

ManualsBrandsNXP SEMICONDUCTORS ManualsLogic ICsLogic IC - Gate and inverter NAND gate 74HC SO 14

1. General description

The 74HC20; 74HCT20 is a dual 4-input NAND gate. Inputs include clamp diodes. This

enables the use of current limiting resistors to interface inputs to voltages in excess of

2. Features and benefits

 Complies with JEDEC standard JESD7A

 Low-power dissipation

 Input levels:

 For 74HC20: CMOS level

 For 74HCT20: TTL level

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 Multiple package options

 Specified from 40 Cto+80C and from 40 Cto+125C.

3. Ordering information

74HC20; 74HCT20

Dual 4-input NAND gate

Rev. 3 — 3 September 2012 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74HC20N 40 C to +125 C DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1

74HCT20N

74HC20D 40 C to +125 C SO14 plastic small outline package; 14 leads; body width

3.9 mm

SOT108-1

74HCT20D

74HC20DB 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body

width 5.3 mm

SOT337-1

74HCT20DB

74HC20PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74HCT20PW

Summary of content (16 pages)

PAGE 1
74HC20; 74HCT20 Dual 4-input NAND gate Rev. 3 — 3 September 2012 Product data sheet 1. General description The 74HC20; 74HCT20 is a dual 4-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 4. Functional diagram $ % < & ' $ % < & ' DDD Fig 1. Functional diagram Fig 2. $ % < & ' $ % < & ' DDD Logic symbol $ % < & ' DDD Fig 3. IEC Logic symbol Fig 4. DDD Logic diagram 5. Pinning information 5.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A, 1B, 1C, 1D 1, 2, 4, 5 data input n.c. 3, 11 not connected 1Y 6 data output GND 7 ground (0 V) 2Y 8 data output 2A, 2B, 2C, 2D 9, 10, 12, 13 data input VCC 14 supply voltage 6. Functional description Table 3.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC20 Min 74HCT20 Typ Max Min Unit Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions Min CI input capacitance Typ 40 C to +85 C 40 C to +125 C Unit Max Min Max Min Max - 3.5 - - - - - pF 74HCT20 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for load circuit see Figure 8. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) 74HC20 propagation delay nA, nB, nC or nD to nY; see Figure 7 tpd [1] VCC = 2.0 V - 28 90 115 135 ns VCC = 4.5 V - 10 18 23 27 ns VCC = 6.0 V - 8 15 20 23 ns - 8 - - - ns VCC = 2.
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4HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 11. Waveforms 9, Q$ Q% Q& Q' LQSXW 90 *1' W3+/ 92+ W3/+ 9< 90 Q< RXWSXW 9; 92/ W7+/ W7/+ DDD Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. Waveforms showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output transition times Measurement points Type Input Output VM VM VX VY 74HC20 0.5VCC 0.5VCC 0.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate Table 9. Test data Type Input Load Test VI tr, tf CL 74HC20 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HCT20 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HC_HCT20 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 3 — 3 September 2012 © NXP B.V. 2012. All rights reserved.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 12. Package outline DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 ME seating plane D A2 A A1 L c e Z w M b1 (e 1) b MH 8 14 pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 min. A2 max. b b1 c D (1) E (1) e e1 L ME MH w Z (1) max. mm 4.2 0.51 3.2 1.73 1.13 0.53 0.38 0.36 0.23 19.50 18.55 6.48 6.20 2.54 7.62 3.
PAGE 10
74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm D SOT337-1 E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp L 7 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT20 v.3 20120903 Product data sheet - 74HC_HCT20_CNV v.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use.
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74HC20; 74HCT20 NXP Semiconductors Dual 4-input NAND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . .