Datasheet

December 1990 7
Philips Semiconductors Product specification
9-bit odd/even parity generator/checker 74HC/HCT280
AC WAVEFORMS
APPLICATION INFORMATION
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines” .
Fig.6 Waveforms showing the data input (I
n
) to parity outputs (∑
E
, ∑
O
) propagation delays and the output
transition time.
(1) HC : V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7 Cascaded 17-bit odd/even parity generator/checker.
For a single-chip 16-bit even/odd parity
generator/checker, see PC74HC/HCT7080.